公开(公告)号：US20090286770A1

公开(公告)日：2009-11-19

申请号：US11721094

申请日：2005-12-07

申请人： D. Gary Gilliland ,  James Douglas Griffin ,  Jing Chen ,  Kenneth C. Anderson

发明人： D. Gary Gilliland ,  James Douglas Griffin ,  Jing Chen ,  Kenneth C. Anderson

IPC分类号： A61K31/553 ,  C07D245/06 ,  A61P35/00

CPC分类号： A61K31/407 ,  A61K31/553

摘要： The present invention relates to the use of staurosporines derivatives for the preparation of a drug for the treatment of diseases involving ras or FGFR3 signalling pathways and l or c-fos transcription, especially for the curative and/or prophylactic treatment of myeloma or multiple Myeloma, and to a method of treating diseases involving ras or FGFR3 signalling pathways and/or c-fos transcription.

摘要翻译： 本发明涉及星形孢菌素衍生物用于制备用于治疗涉及ras或FGFR3信号传导途径和l或c-fos转录的疾病的药物的用途，特别是用于治疗和/或预防性治疗骨髓瘤或多发性骨髓瘤， 以及治疗涉及ras或FGFR3信号传导途径和/或c-fos转录的疾病的方法。

公开(公告)号：US20140294818A1

公开(公告)日：2014-10-02

申请号：US14349550

申请日：2012-10-11

申请人： Jing Chen ,  Taro Hitosugi ,  Sumin Kang

发明人： Jing Chen ,  Taro Hitosugi ,  Sumin Kang

IPC分类号： C07C311/29 ,  A61K45/06 ,  C07K16/40 ,  A61K31/18

CPC分类号： C07C311/29 ,  A61K31/18 ,  A61K45/06 ,  C07C2603/24 ,  C07K16/40 ,  C07K2317/34 ,  C09B1/06 ,  C09B1/12

摘要： In certain embodiments, the disclosure relates to methods of treating or preventing a PGAM1 mediated condition such as cancer or tumor growth comprising administering an effective amount of PGAM1 inhibitor, for example, an anthracene-9,10-dione derivative to a subject in need thereof. In certain embodiments, the disclosure relates to methods of treating or preventing cancer, such as lung cancer, head and neck cancer, and leukemia, comprising administering a therapeutically effective amount of a pharmaceutical composition comprising a compound disclosed herein or pharmaceutically acceptable salt to a subject in need thereof.

摘要翻译： 在某些实施方案中，本公开涉及治疗或预防PGAM1介导的病症如癌症或肿瘤生长的方法，包括向有需要的受试者施用有效量的PGAM1抑制剂，例如蒽-9,10-二酮衍生物 。 在某些实施方案中，本公开涉及治疗或预防癌症的方法，例如肺癌，头颈癌和白血病，包括向受试者施用治疗有效量的包含本文公开的化合物或药学上可接受的盐的药物组合物 需要它。

公开(公告)号：US08502323B2

公开(公告)日：2013-08-06

申请号：US12185241

申请日：2008-08-04

申请人： Jing Chen

发明人： Jing Chen

IPC分类号： H01L21/20

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316

摘要： A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress.

摘要翻译： 场效应晶体管包括第一栅极，保持在共源共栅配置中基本上固定的电位的第二栅极和半导体沟道。 半导体通道具有增强模式部分和耗尽模式部分。 增强模式部分通过第一门选通和导通，并被修改为在增强模式下工作。 耗尽模式部分由第二栅极选通，并且已被修改为在耗尽模式下工作，并且可操作地屏蔽第一栅极免受电压应力。

公开(公告)号：US20130092958A1

公开(公告)日：2013-04-18

申请号：US13699296

申请日：2010-09-08

申请人： Jing Chen ,  Li Yuan ,  Hongwei Chen ,  Chunhua Zhou

发明人： Jing Chen ,  Li Yuan ,  Hongwei Chen ,  Chunhua Zhou

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/16

CPC分类号： H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/872 ,  H01L29/88 ,  H01L2224/06181 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/00

摘要： Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.

摘要翻译： 提供了用于产生异质结AlGaN / GaN金属二维电子气（2DEG）隧道结场效应晶体管（TJ-FET）的结构，器件和方法。 在一方面，金属2DEG肖特基隧道结可以用于能够进行常关断操作，大的击穿电压，低漏电流和高导通/截止电流比的III-N型氮化物场效应器件中。 作为另外的优点，公开了可以以横向配置和/或垂直配置制造的AlGaN / GaN金属2DEG TJ-FET。 提供了另外的非限制性实施例，其示出了所公开的结构的优点和灵活性。

公开(公告)号：US20130054210A1

公开(公告)日：2013-02-28

申请号：US13696455

申请日：2011-09-25

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

IPC分类号： G06F17/10

CPC分类号： G01R31/2628 ,  G01R31/2603 ,  G06F17/5036

摘要： The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model.

摘要翻译： 本发明提供了一种用于确定BSIMSOI4直流（DC）模型参数的方法，其中，体内引出结构和不同尺寸的多个金属氧化物半导体场效应晶体管（MOSFET）器件和多个MOSFET器件 提供浮动结构和不同尺寸; 所有MOSFET器件的Id-Vg-Vp，Id / Ip-Vd-Vg，Ig-Vg-Vd，Ig-Vp，Ip-Vg-vd，Is / Id-Vp和Id / Ip-Vp-Vd特性 测量浮体结构的所有MOSFET器件的体导体结构和Id-Vg-Vp，Id-Vd-Vg和Ig-Vg-Vd特性; 获得不具有体引出结构的每个MOSFET器件和浮置结构的每个MOSFET器件的自发热效应的电性能曲线; 然后根据具体步骤依次提取BSIMSOI4模型的DC参数。 在本发明中，根据模型方程依次选择适当的试验曲线，并连续确定各种参数，从而准确有效地提取BSIMSOI4型号的直流参数。

公开(公告)号：US08373533B2

公开(公告)日：2013-02-12

申请号：US12851237

申请日：2010-08-05

申请人： Han Li ,  Gang Liu ,  Jing Chen ,  Jinfa Zhang

发明人： Han Li ,  Gang Liu ,  Jing Chen ,  Jinfa Zhang

IPC分类号： H01F27/29

CPC分类号： H05K7/1432 ,  H01F27/292 ,  H01F2027/408 ,  H02M3/33592 ,  Y02B70/1475

摘要： A power module includes a first bobbin, a primary winding coil, a circuit board assembly and a first magnetic core assembly. The primary winding coil is wound around the first bobbin. The circuit board assembly includes a printed circuit board, a second winding structure, at least one current-sensing element, a rectifier circuit and an electrical connector. The second winding structure has an output terminal. The current-sensing element includes a first conductor. The first conductor is a conductive sheet. A first end of the first conductor is in contact with the output terminal of the second winding structure. A second end of the first conductor is connected to the rectifier circuit. The primary winding coil is aligned with the second winding structure of the circuit board assembly and arranged within the first magnetic core assembly. The primary winding coil and the electrical connector are electrically connected with a system board.

摘要翻译： 功率模块包括第一线圈架，初级绕组线圈，电路板组件和第一磁芯组件。 初级绕组线圈缠绕在第一线轴上。 电路板组件包括印刷电路板，第二绕组结构，至少一个电流感测元件，整流器电路和电连接器。 第二绕组结构具有输出端子。 电流检测元件包括第一导体。 第一导体是导电片。 第一导体的第一端与第二绕组结构的输出端接触。 第一导体的第二端连接到整流电路。 初级绕组线圈与电路板组件的第二绕组结构对准并且布置在第一磁芯组件内。 初级绕组线圈和电连接器与系统板电连接。

公开(公告)号：US08264042B2

公开(公告)日：2012-09-11

申请号：US12810574

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/42392

摘要： A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

摘要翻译： 混合取向累积模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Si（110）和n型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在积累模式中，电流流过整个跑道状通道。 所公开的装置导致高载流子迁移率。 同时防止多晶硅栅极耗尽和短沟道效应，并且阈值电压增加。

公开(公告)号：US08255857B2

公开(公告)日：2012-08-28

申请号：US12347871

申请日：2008-12-31

申请人： Limin He ,  So-Zen Yao ,  Wenyong Deng ,  Jing Chen ,  Liang-Jih Chao

发明人： Limin He ,  So-Zen Yao ,  Wenyong Deng ,  Jing Chen ,  Liang-Jih Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。

公开(公告)号：US08254686B2

公开(公告)日：2012-08-28

申请号：US12276284

申请日：2008-11-21

申请人： Jiaming He ,  Jianfen Wen ,  Dexiang Jia ,  Jing Chen ,  Ping Chen ,  Chengchen Ma ,  Zhouyi Fan ,  Hongzhen Ding ,  Zhihui Shi ,  Aijun Shi ,  Linghui Fan

发明人： Jiaming He ,  Jianfen Wen ,  Dexiang Jia ,  Jing Chen ,  Ping Chen ,  Chengchen Ma ,  Zhouyi Fan ,  Hongzhen Ding ,  Zhihui Shi ,  Aijun Shi ,  Linghui Fan

IPC分类号： G06K9/00 ,  G06K9/18 ,  G06K9/34 ,  G06K9/48 ,  G06K7/10 ,  G06K9/20 ,  G09G1/10

CPC分类号： G06K9/00409 ,  G06K9/00422

摘要： The present invention discloses an on-line identifying method of hand-written Arabic letter. The advantage of the present invention is that the multilayer coarse classification algorithm based on the local characteristic of Arabic letter fully utilize the various local characteristics of Arabic letter, obtain the first candidate letter aggregation matching with the inputted hand-written Arabic letter according to the first level coarse classification formed by the stroke number of letter, and then obtain the second candidate letter aggregation matching with inputted hand-written Arabic letter according to the other local characteristics and the first candidate letter aggregation. The application of the algorithm enables that the inputted hand-written Arabic letter only need to match with the standard letter stored in the predetermined letter library and the corresponding standard letters of the second candidate letter aggregation.

摘要翻译： 本发明公开了一种手写阿拉伯信的在线识别方法。 本发明的优点是，基于阿拉伯语的本地特征的多层粗分类算法充分利用了阿拉伯语字的各种局部特征，根据第一个字母获得与输入的手写阿拉伯语字母的第一候选字母聚合匹配 根据其他本地特征和第一候选字母聚合获得与输入的手写阿拉伯语字母的第二候选字母聚合匹配。 该算法的应用使得输入的手写阿拉伯语字母仅需要与存储在预定字母库中的标准字母和第二候选字母聚合的相应标准字母匹配。

公开(公告)号：US08233312B2

公开(公告)日：2012-07-31

申请号：US12934745

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/24

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的第一N型半导体区域，设置在第一N型半导体区域上的P型半导体区域，设置在P型半导体区域上的栅极区域和围绕P型半导体区域的电隔离区域 型半导体区域和N型半导体区域。 二极管作为存储节点。 通过带之间的隧道效应，孔被聚集在浮体中，其被定义为第一储存状态; 通过PN结的正向偏压，空穴从浮体发射出来，或者电子被注入浮动体，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。