公开(公告)号：US20070298524A1

公开(公告)日：2007-12-27

申请号：US11425913

申请日：2006-06-22

申请人： DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

发明人： DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  G03F7/70658 ,  H01L22/12

摘要： The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

摘要翻译： 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。

公开(公告)号：US07504270B2

公开(公告)日：2009-03-17

申请号：US11425913

申请日：2006-06-22

申请人： David D. Wu ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

发明人： David D. Wu ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

IPC分类号： G10R31/26 ,  H01L21/66

CPC分类号： H01L22/34 ,  G03F7/70658 ,  H01L22/12

摘要： The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

摘要翻译： 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。

公开(公告)号：US20090090969A1

公开(公告)日：2009-04-09

申请号：US11867743

申请日：2007-10-05

申请人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

发明人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

摘要翻译： 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US08687417B2

公开(公告)日：2014-04-01

申请号：US11867743

申请日：2007-10-05

申请人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Akif Sultan ,  Fred Hause ,  Donna Michael

发明人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Akif Sultan ,  Fred Hause

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/02 ,  G11C16/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

摘要翻译： 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US07793240B2

公开(公告)日：2010-09-07

申请号：US11537390

申请日：2006-09-29

申请人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

发明人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

摘要翻译： 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。

公开(公告)号：US20080104550A1

公开(公告)日：2008-05-01

申请号：US11537390

申请日：2006-09-29

申请人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

发明人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

摘要翻译： 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。

公开(公告)号：US07670938B2

公开(公告)日：2010-03-02

申请号：US11381219

申请日：2006-05-02

申请人： David D. Wu ,  Mark W. Michael

发明人： David D. Wu ,  Mark W. Michael

IPC分类号： H01L21/44

CPC分类号： H01L21/76819 ,  H01L21/76802 ,  H01L21/76834 ,  H01L29/7843

摘要： The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original height of the layer stack to thereby define a reduced height layer stack above the feature, forming an opening in the reduced height layer stack for a conductive member that will be electrically coupled to the feature and forming the conductive member in the opening in the reduced height layer stack.

摘要翻译： 本发明涉及形成接触开口的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成特征，形成由特征上方的多层材料构成的层叠层，层堆叠具有原始高度，从而降低层堆叠的原始高度 在所述特征之上限定减小的高度层堆叠，在所述减小的高度层堆叠中形成用于导电构件的开口，所述导电构件将电耦合到所述特征并且在所述还原高度层堆叠中的所述开口中形成所述导电构件。

公开(公告)号：US20070296444A1

公开(公告)日：2007-12-27

申请号：US11426723

申请日：2006-06-27

申请人： Jianhong Zhu ,  David D. Wu ,  Mark W. Michael

发明人： Jianhong Zhu ,  David D. Wu ,  Mark W. Michael

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/2648

摘要： A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of fingers extending from the second base. At least a portion of the first and second pluralities of fingers are interleaved. The first pair of base nodes extend from the first base. The second pair of finger nodes extend from a first finger of the first plurality of fingers.

摘要翻译： 测试结构包括第一和第二梳，至少第一对基本节点和第二对​​手指节点。 第一梳子包括从第一基部延伸的第一基部和第一多个指状物。 第二梳子包括从第二基部延伸的第二基部和第二多个指状物。 第一和第二多个手指的至少一部分交错。 第一对基本节点从第一个基地延伸。 所述第二对手指节点从所述第一多个手指的第一手指延伸。

公开(公告)号：US07355201B2

公开(公告)日：2008-04-08

申请号：US11426723

申请日：2006-06-27

申请人： Jianhong Zhu ,  David D. Wu ,  Mark W. Michael

发明人： Jianhong Zhu ,  David D. Wu ,  Mark W. Michael

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  G01R31/2648

摘要： A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of fingers extending from the second base. At least a portion of the first and second pluralities of fingers are interleaved. The first pair of base nodes extend from the first base. The second pair of finger nodes extend from a first finger of the first plurality of fingers.

摘要翻译： 测试结构包括第一和第二梳，至少第一对基本节点和第二对​​手指节点。 第一梳子包括从第一基部延伸的第一基部和第一多个指状物。 第二梳子包括从第二基部延伸的第二基部和第二多个指状物。 第一和第二多个手指的至少一部分交错。 第一对基本节点从第一个基地延伸。 所述第二对手指节点从所述第一多个手指的第一手指延伸。

公开(公告)号：US06552776B1

公开(公告)日：2003-04-22

申请号：US09183176

申请日：1998-10-30

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

IPC分类号： G03B2754

CPC分类号： G03F7/70558 ,  G03F7/70191 ,  G03F7/706

摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。