公开(公告)号：US20160336251A1

公开(公告)日：2016-11-17

申请号：US15149240

申请日：2016-05-09

Applicant: DENSO CORPORATION

Inventor： Daisuke FUKUOKA

IPC: H01L23/367 ,  H01L29/739 ,  H02M7/44 ,  H01L29/16 ,  H01L27/06 ,  H01L23/31 ,  H01L29/861

CPC classification number: H02M7/44 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L27/0664 ,  H01L27/0727 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/861 ,  H01L2224/33 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor chip, a metal member, and a terminal. The semiconductor chip has an electrode. The metal member is electrically connected to the electrode. The terminal extends from the metal member to be connected to an external connection member. The terminal has a width-increased portion in a predetermined area beginning from a first end of the terminal that connects to the metal member.

Abstract translation: 半导体器件包括半导体芯片，金属构件和端子。 半导体芯片具有电极。 金属构件电连接到电极。 端子从金属构件延伸以连接到外部连接构件。 端子在从连接到金属构件的端子的第一端开始的预定区域中具有宽度增加部分。

公开(公告)号：US20200211954A1

公开(公告)日：2020-07-02

申请号：US16814260

申请日：2020-03-10

Applicant: DENSO CORPORATION

Inventor： Tomoo IWADE ,  Daisuke FUKUOKA

IPC: H01L23/50 ,  H01L23/52 ,  H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H02M7/00

Abstract: A semiconductor module includes a plurality of semiconductor elements, a sealing resin body, a positive electrode side terminal, a negative electrode side terminal, and an output terminal. The positive electrode side terminal, the negative electrode side terminal, and the output terminal are each connected to any of the semiconductor elements, and project from a same surface of the sealing resin body. Projecting portions of the positive electrode side terminal, the negative electrode side terminal, and the output terminal are arranged next to each other in an arrangement direction so that the projecting portion of the output terminal is located at an end.

公开(公告)号：US20180323125A1

公开(公告)日：2018-11-08

申请号：US15772116

申请日：2017-03-13

Applicant: DENSO CORPORATION

Inventor： Shuji YONEDA ,  Daisuke FUKUOKA ,  Eiji HAYASHI

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/28 ,  H01L23/48 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/33 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00012

Abstract: In an electronic device, an inner lead of a signal terminal includes a base member, and a film on a surface of the inner lead adjacent to a bonding surface. The film includes a metal thin film disposed on the surface of the base member and having a portion to which a bonding wire is connected, and an oxide film made of an oxide of the same metal as a metal being a main component of the metal thin film, and disposed in at least a part of a region of the metal thin film, excluding a connection region of a bonding wire. The oxide film includes an uneven oxide film having a surface with continuous asperities formed by irradiating the metal thin film with pulsed laser light. The uneven oxide film is disposed in at least a part of a front end region of the bonding surface.

公开(公告)号：US20220223544A1

公开(公告)日：2022-07-14

申请号：US17708525

申请日：2022-03-30

Applicant: DENSO CORPORATION

Inventor： Daisuke FUKUOKA ,  Tomomi OKUMURA ,  Yuuji OOTANI ,  Wataru KOBAYASHI ,  Takumi NOMURA ,  Tomoaki MITSUNAGA ,  Takahiro HIRANO ,  Takamichi SAKAI ,  Kengo OKA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48

Abstract: In a semiconductor device, a semiconductor element has a front electrode and a back electrode. The back electrode is connected to a wiring member through a bonding member. Wire pieces are disposed in the bonding member, and bonded to a bonding surface of the wiring member to protrude toward the semiconductor element. The bonding member has, in a plan view, a central region that overlaps with a central portion of the semiconductor element including an element center, and an outer peripheral region that includes a portion overlapping with an outer peripheral portion of the semiconductor element surrounding the central portion and surrounds the central region. At least four wire pieces are disposed in the outer peripheral region at positions corresponding to at least four respective corners of the semiconductor element. At least one wire piece is disposed to extend toward the element center in the plan view.