公开(公告)号：US20250040205A1

公开(公告)日：2025-01-30

申请号：US18912081

申请日：2024-10-10

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of p-type deep layers, a plurality of n-type deep layers, a drift layer of n-type, and an n-type high concentration layer. The n-type high concentration layer is in contact with at least a part of a lower surface of a corresponding p-type deep layer in the plurality of p-type deep layers and has a higher concentration of n-type impurities than the drift layer.

公开(公告)号：US20240258425A1

公开(公告)日：2024-08-01

申请号：US18632840

申请日：2024-04-11

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0603 ,  H01L29/1608 ,  H01L29/66734

Abstract: A semiconductor device includes a semiconductor layer, and a trench gate. The semiconductor layer has a drift region of a first conductivity type and a body region of a second conductivity type. The trench gate is disposed in a trench that extends from a first main surface of the semiconductor layer to the drift region through the body region. A side surface of the trench gate is in contact with the body region and the drift region. Of the body region and the drift region, only the body region has a channel region in a portion in contact with the side surface of the trench gate, and the channel region has an impurity concentration lower than an impurity concentration of a portion of the body region further from the side surface of the trench gate.

公开(公告)号：US20250089293A1

公开(公告)日：2025-03-13

申请号：US18955087

申请日：2024-11-21

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423

Abstract: A field effect transistor includes: a semiconductor substrate having a trench; a gate insulating film; and a gate electrode. The semiconductor substrate has a p-type body layer and a lower n-layer. The lower n-layer has: a current spreading n-layer in contact with the body layer; and a low-concentration n-layer in contact with the current spreading n-layer and having a lower n-type impurity concentration than the current spreading n-layer. An inner surface of the trench has a side surface having a radius of curvature of 0.7 μm or more, and a bottom connection surface connecting the side surface to a lower end of the trench and formed by a concave curved surface having a radius of curvature of less than 0.7 μm. A portion of the current spreading n-layer having the peak value is in contact with the gate insulating film on the side surface.

公开(公告)号：US20230387194A1

公开(公告)日：2023-11-30

申请号：US18446919

申请日：2023-08-09

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0615 ,  H01L29/7813 ,  H01L29/66734

Abstract: A field effect transistor includes a p-type trench lower layer, multiple p-type deep layers, and multiple n-type deep layers. The p-type trench lower layer is located below the trench, and extends in a longitudinal direction of the trench in a top view of a semiconductor substrate. Each of the p-type deep layers protrudes downward from a body layer, and extends in a first direction intersecting the trench in the top view of the semiconductor substrate. The p-type deep layers are spaced at intervals in a second direction perpendicular to the first direction, and are in contact with the p-type trench lower layer located below the trench. Each of the n-type deep layers is located in corresponding one of the intervals, and is in contact with a gate insulating film at a side surface of the trench located below the body layer.

公开(公告)号：US20230369484A1

公开(公告)日：2023-11-16

申请号：US18358992

申请日：2023-07-26

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA

IPC: H01L29/78

CPC classification number: H01L29/7811 ,  H01L29/7813

Abstract: A field effect transistor includes a plurality of p-type deep layers. The p-type deep layers protrude downward from a body layer, extend so as to intersect a trench when a semiconductor substrate is viewed from above, and extend from the body layer to a position below a bottom surface of the trench. Each of the p-type deep layers includes a low concentration region and a high concentration region having a higher p-type impurity concentration than the low concentration region and the body layer. The low concentration region is in contact with the body layer from below, and is in contact with the gate insulating film on a side surface of the trench located below the body layer. The high concentration region is in contact with the low concentration region from below.

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

Applicant: Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20220102485A1

公开(公告)日：2022-03-31

申请号：US17546248

申请日：2021-12-09

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA ,  Yuichi TAKEUCHI ,  Yukihiko WATANABE

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

公开(公告)号：US20180151366A1

公开(公告)日：2018-05-31

申请号：US15570841

申请日：2016-04-05

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Takeshi ENDO ,  Atsuya AKIBA ,  Yuichi TAKEUCHI ,  Hidefumi TAKAYA ,  Sachiko AOI

IPC: H01L21/20 ,  H01L29/78 ,  H01L29/16 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L21/2003 ,  H01L21/046 ,  H01L21/265 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/78

Abstract: A semiconductor device includes: a substrate having a cell region with a semiconductor element and an outer peripheral region; and a drift layer on the substrate. The semiconductor element includes a base region, a source region, a trench gate structure, a deep layer deeper than a gate trench, a source electrode, and a drain electrode. The outer peripheral region has a recess portion in which the drift layer are exposed, and a guard ring layer. The guard ring layer includes multiple guard ring trenches having a frame shape, surrounding the cell region and arranged on an exposed surface of the drift layer, and a first guard ring in the guard ring trenches. Each of the linear deep trenches has a width equal to a width of each of the linear guard ring trenches.

公开(公告)号：US20170018643A1

公开(公告)日：2017-01-19

申请号：US15124326

申请日：2015-02-10

Applicant: Toyota Jidosha Kabushiki Kaisha ,  Denso Corporation

Inventor： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Toshimasa YAMAMOTO ,  Narumasa SOEJIMA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/761 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L21/761 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.

Abstract translation: 本文提供的半导体器件包括：p型的第四区域与栅极沟槽的下端接触; 在第二区域外的范围内设置在前表面的终端沟槽; p型的下端p型区域与端接沟槽的下端接触; p型侧面p型区域与外周侧的终端沟槽的侧面接触，与下端p型区域连接并露出在前表面上; 以及相对于侧面p型区域在外周侧设置并暴露在前表面上的多个保护环区域。

公开(公告)号：US20150171175A1

公开(公告)日：2015-06-18

申请号：US14557662

申请日：2014-12-02

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hidefumi TAKAYA ,  Yukihiko WATANABE ,  Sachiko AOI ,  Atsuya AKIBA

IPC: H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes: a drift layer having a first conductivity type; a body layer having a second conductivity type; a first semiconductor region having the first conductivity type; a gate insulation film; a trench gate electrode; a first main electrode; a second semiconductor region having the second conductivity type; and a conductor region. The first main electrode is electrically connected with the body layer and the first semiconductor region. The second semiconductor region is disposed on a bottom part of the gate trench, and is surrounded by the drift layer. The conductor region is configured to electrically connect the first main electrode with the second semiconductor region and is configured to equalize, when the semiconductor device is in an off-state, a potential of the second semiconductor region and a potential of the first main electrode.

Abstract translation: 半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型的主体层; 具有第一导电类型的第一半导体区; 栅极绝缘膜; 沟槽栅电极; 第一主电极; 具有第二导电类型的第二半导体区; 和导体区域。 第一主电极与主体层和第一半导体区电连接。 第二半导体区域设置在栅极沟槽的底部，被漂移层包围。 导体区域被配置为将第一主电极与第二半导体区域电连接，并且被配置为当半导体器件处于截止状态时使第二半导体区域的电位和第一主电极的电位相等。