公开(公告)号：US09634095B2

公开(公告)日：2017-04-25

申请号：US14759823

申请日：2013-12-23

Applicant: DENSO CORPORATION

Inventor： Seigo Oosawa ,  Yutaka Tomatsu ,  Masahiro Ogino ,  Tomomi Oobayashi

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7813

Abstract: In a semiconductor device, a first conductivity-type first semiconductor region that abuts on a side surface of a contact trench adjacent to an opening portion of the contact trench, and has a higher impurity concentration than that of a second semiconductor layer is formed. Also, a second conductivity-type second semiconductor region that abuts on a bottom surface of the contact trench and a side surface of the contact trench adjacent to the bottom surface of the contact trench, and has a higher impurity concentration than that of a first semiconductor layer is formed. A first electrode that is connected electrically with the first semiconductor region and the second semiconductor region is disposed in the contact trench. Even when the semiconductor device is miniaturized by reducing the width of the contact trench, a breakage of the semiconductor device when switched from an on-state to an off-state is reduced.

公开(公告)号：US09171906B2

公开(公告)日：2015-10-27

申请号：US14278430

申请日：2014-05-15

Applicant: DENSO CORPORATION

Inventor： Eiichi Taketani ,  Seigo Oosawa

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L21/26586 ,  H01L21/28211 ,  H01L29/0626 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7813

Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.

Abstract translation: 在半导体器件的制造方法中，在半导体衬底中限定沟槽，并且在与半导体衬底的底壁相邻的半导体衬底的一部分处形成具有高于漂移层的第一导电类型杂质浓度的调节器层 沟。 通过在半导体衬底的与沟槽的侧壁相邻的部分和调整层与半导体衬底的主表面之间以及在半导体衬底的主表面之间引入第二导电类型的杂质形成沟道层，同时限制沟道层在深度方向上延伸 沟槽由调整层。

公开(公告)号：US10109727B2

公开(公告)日：2018-10-23

申请号：US15531015

申请日：2015-12-08

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama ,  Yasushi Higuchi ,  Seigo Oosawa ,  Masaki Matsui ,  Youngshin Eum

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L29/06 ,  H01L29/51 ,  H01L29/40 ,  H01L29/423 ,  H01L29/20

Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.