公开(公告)号：US09202726B2

公开(公告)日：2015-12-01

申请号：US14159055

申请日：2014-01-20

Applicant: DENSO CORPORATION

Inventor： Yoshinori Tsuchiya ,  Shinichi Hoshi ,  Masaki Matsui

IPC: H01L21/302 ,  H01L21/67 ,  H01L21/311 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L21/67069 ,  H01J37/321 ,  H01J2237/334 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7787

Abstract: A manufacturing method of a semiconductor device including arranging a compound semiconductor above a stage of a chamber, supplying an etching gas into the chamber, and generating a plasma in the chamber is provided. The compound semiconductor includes a group-III element nitride as a main component. A surface of the compound semiconductor is processed by a dry etching. Light is irradiated into the chamber during the generating of the plasma. A dry etching apparatus including a chamber including a stage, on which a compound semiconductor is mounted, and a light source irradiating light into the chamber is provided. The chamber is supplied with an etching gas. A plasma is generated in the chamber. A surface of the compound semiconductor is an object of a dry etching.

Abstract translation: 提供一种半导体器件的制造方法，其包括将化合物半导体放置在室的阶段之上，将蚀刻气体供应到所述室中，以及在所述室中产生等离子体。 化合物半导体包括III族元素氮化物作为主要成分。 化学半导体的表面通过干蚀刻进行处理。 在产生等离子体期间，光被照射到腔室中。 提供了一种干蚀刻装置，其包括具有其上安装有化合物半导体的平台的腔室和将光照射到腔室中的光源。 该室被供应蚀刻气体。 在室内产生等离子体。 化合物半导体的表面是干蚀刻的目的。

公开(公告)号：US20150115314A1

公开(公告)日：2015-04-30

申请号：US14381238

申请日：2013-03-04

Applicant: DENSO CORPORATION

Inventor： Kazuki Arakawa ,  Masakiyo Sumitomo ,  Masaki Matsui ,  Yasushi Higuchi ,  Kazuhiro Oyama

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/42376 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7397

Abstract: In a semiconductor device, a trench includes a first trench that has an opening portion on a surface of a base layer, and a second trench that is communicated with the first trench and in which a distance between opposed side walls is greater than opposed side walls of the first trench and a bottom portion is located in a drift layer. A wall surface of a connecting portion of the second trench connecting to the first trench is rounded. Therefore, an occurrence of a large electrical field concentration in the vicinity of the connecting portion between the first trench and the second trench can be suppressed. Also, when electrons are supplied from a channel region to the drift layer, it is less likely that a flow direction of the electrons will be sharply changed in the vicinity of the connecting portion. Therefore, an on-state resistance can be reduced.

Abstract translation: 在半导体器件中，沟槽包括在基底层的表面上具有开口部分的第一沟槽和与第一沟槽连通并且相对的侧壁之间的距离大于相对侧壁的第二沟槽 的第一沟槽和底部部分位于漂移层中。 连接到第一沟槽的第二沟槽的连接部分的壁表面是圆形的。 因此，可以抑制在第一沟槽和第二沟槽之间的连接部分附近出现大的电场集中。 此外，当从沟道区域向漂移层提供电子时，在连接部附近电子的流动方向不会急剧变化。 因此，可以降低导通电阻。

公开(公告)号：US10084052B2

公开(公告)日：2018-09-25

申请号：US15514167

申请日：2015-09-14

Applicant: DENSO CORPORATION

Inventor： Yoshinori Tsuchiya ,  Shinichi Hoshi ,  Masaki Matsui ,  Kenji Itoh

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/786

Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm−2 and allows a normally-off element to be reliably provided.

公开(公告)号：US20150053996A1

公开(公告)日：2015-02-26

申请号：US14389185

申请日：2012-11-01

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  DENSO CORPORATION

Inventor： Tetsuo Narita ,  Kenji Ito ,  Kazuyoshi Tomita ,  Nobuyuki Otake ,  Shinichi Hoshi ,  Masaki Matsui

IPC: H01L29/20 ,  C30B29/40 ,  C30B25/18 ,  C30B25/08 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L29/2003 ,  C30B25/08 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/0254 ,  H01L29/045 ,  H01L33/007

Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.

Abstract translation: 促进了硅单晶衬底上的III族氮化物单晶的阶跃流生长。 在硅单晶衬底的表面上形成定向为硅单晶的<111>轴的氧化物层，并且III族氮化物单晶在氧化物层的表面上结晶。 因此，经历晶体生长的III族氮化物单晶的<0001>轴取向为氧化物的c轴。 当硅单晶衬底具有误差角时，发生III族氮化物单晶的阶跃流生长。 通过对形成在硅单晶和氧化物的界面处的氧化硅层进行脱氧，氧化物的取向得到改善。

公开(公告)号：US20150048413A1

公开(公告)日：2015-02-19

申请号：US14386132

申请日：2013-05-13

Applicant: DENSO CORPORATION

Inventor： Kazuki Arakawa ,  Masakiyo Sumitomo ,  Masaki Matsui ,  Yasushi Higuchi

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes: a drift layer; a base layer arranged in a surface portion of the drift layer; multiple trenches penetrating the base layer and reaching the drift layer; and a gate electrode arranged on the gate insulation film in each trench. Each trench includes: a first trench having an opening on a surface of the base layer; and a second trench connecting the first trench and having a portion, of which a distance between facing sidewalls of the second trench is longer than a distance between facing sidewalls of the first trench. The opening of each first trench is sealed with the gate electrode. An inside of each gate electrode includes a cavity portion.

Abstract translation: 半导体器件包括：漂移层; 布置在所述漂移层的表面部分中的基底层; 多个沟槽穿透基层并到达漂移层; 以及在每个沟槽中布置在栅极绝缘膜上的栅电极。 每个沟槽包括：在基底层的表面上具有开口的第一沟槽; 以及第二沟槽，其连接所述第一沟槽并具有一部分，所述第二沟槽的所述第二沟槽的相对侧壁之间的距离比所述第一沟槽的相对侧壁之间的距离长。 每个第一沟槽的开口用栅电极密封。 每个栅电极的内部包括空腔部分。

公开(公告)号：US10109727B2

公开(公告)日：2018-10-23

申请号：US15531015

申请日：2015-12-08

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama ,  Yasushi Higuchi ,  Seigo Oosawa ,  Masaki Matsui ,  Youngshin Eum

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L29/06 ,  H01L29/51 ,  H01L29/40 ,  H01L29/423 ,  H01L29/20

Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.

公开(公告)号：US09728609B2

公开(公告)日：2017-08-08

申请号：US14389185

申请日：2012-11-01

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  DENSO CORPORATION

Inventor： Tetsuo Narita ,  Kenji Ito ,  Kazuyoshi Tomita ,  Nobuyuki Otake ,  Shinichi Hoshi ,  Masaki Matsui

IPC: H01L29/15 ,  H01L29/20 ,  C30B29/40 ,  H01L21/02 ,  C30B25/08 ,  C30B25/18 ,  H01L29/04 ,  H01L33/00

CPC classification number: H01L29/2003 ,  C30B25/08 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/0254 ,  H01L29/045 ,  H01L33/007

Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.

公开(公告)号：US10121663B2

公开(公告)日：2018-11-06

申请号：US15320799

申请日：2015-03-26

Applicant: DENSO CORPORATION

Inventor： Yoshinori Tsuchiya ,  Hiroyuki Tarumi ,  Shinichi Hoshi ,  Masaki Matsui ,  Kenji Itoh ,  Tetsuo Narita ,  Tetsu Kachi

IPC: H01L21/223 ,  H01L21/20 ,  H01L29/786 ,  H01L29/04 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L21/28 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm−3.