公开(公告)号：US09300461B2

公开(公告)日：2016-03-29

申请号：US14420721

申请日：2013-09-12

Applicant: DENSO CORPORATION

Inventor： Hironobu Akita ,  Shigeki Ohtsuka

IPC: H03D3/24 ,  H04L7/00 ,  H03L7/087 ,  H03L7/22 ,  H04L7/033 ,  H03L7/085

CPC classification number: H04L7/0087 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/22 ,  H04L7/0331 ,  H04L7/0337

Abstract: In a reception circuit, in a first operating mode, the operation of at least a first charge pump circuit of a phase frequency comparator, the first charge pump circuit, samplers other than a specific sampler in samplers provided in a multi-phase sampler, and a data reproducing unit stops. In a second operating mode, the operation of at least a second charge pump circuit of a phase comparator and the second charge pump circuit stops.

Abstract translation: 在接收电路中，在第一操作模式中，至少在相位频率比较器的第一电荷泵电路，第一电荷泵电路，除了在多相采样器中提供的采样器中的特定采样器之外的采样器的操作，以及 数据再现单元停止。 在第二操作模式中，相位比较器和第二电荷泵电路的至少第二电荷泵电路的操作停止。

公开(公告)号：US09197459B1

公开(公告)日：2015-11-24

申请号：US14710724

申请日：2015-05-13

Applicant: DENSO CORPORATION

Inventor： Tetsuya Kusumoto ,  Shigeki Ohtsuka ,  Nobuaki Matsudaira ,  Hironobu Akita

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L2025/0349

Abstract: In a decision feedback equalizer, at least one of weighting devices that has a tap coefficient an absolute value of which is relatively larger than absolute values of tap coefficients of other weighting devices is referred to as a main weighting device, and delay elements are disposed asymmetrically on signal processing paths or updating paths of the tap coefficients of the weighting devices in such a manner that an updating interval of the tap coefficient of the main weighting device is shorter than updating intervals of the tap coefficients of the other weighting devices.

Abstract translation: 在判定反馈均衡器中，具有绝对值的抽头系数相对大于其他加权装置的抽头系数的绝对值的加权装置中的至少一个被称为主加权装置，并且延迟元件被非对称地布置 在加权装置的抽头系数的信号处理路径或更新路径上，使得主加权装置的抽头系数的更新间隔短于其他加权装置的抽头系数的更新间隔。

公开(公告)号：US20150222418A1

公开(公告)日：2015-08-06

申请号：US14420721

申请日：2013-09-12

Applicant: DENSO CORPORATION

Inventor： Hironobu Akita ,  Shigeki Ohtsuka

IPC: H04L7/00 ,  H03L7/085 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/22 ,  H04L7/0331 ,  H04L7/0337

Abstract: In a reception circuit, in a first operating mode, the operation of at least a first charge pump circuit of a phase frequency comparator, the first charge pump circuit, samplers other than a specific sampler in samplers provided in a multi-phase sampler, and a data reproducing unit stops. In a second operating mode, the operation of at least a second charge pump circuit of a phase comparator and the second charge pump circuit stops.

Abstract translation: 在接收电路中，在第一操作模式中，至少在相位频率比较器的第一电荷泵电路，第一电荷泵电路，除了在多相采样器中提供的采样器中的特定取样器之外的采样器的操作，以及 数据再现单元停止。 在第二操作模式中，相位比较器和第二电荷泵电路的至少第二电荷泵电路的操作停止。

公开(公告)号：US10284388B2

公开(公告)日：2019-05-07

申请号：US15744103

申请日：2016-06-13

Applicant: DENSO CORPORATION

Inventor： Tomohisa Kishigami ,  Shigeki Ohtsuka ,  Nobuaki Matsudaira ,  Hironobu Akita

IPC: H04L12/40 ,  H04L25/02 ,  H04L25/03

Abstract: A communication system includes a transmission path and multiple nodes. At least one of the multiple nodes includes a second communication portion and a control portion in addition to a first communication portion. When the control portion performs a high speed communication, the control portion shifts the first communication portion included in each of the remaining multiple nodes to a sleep mode. The second communication portion performs a differential communication at a higher speed than the first communication portion using a differential signal. In the differential signal, a maximum of a potential difference between the pair of communication lines is equal to or less than a recessive threshold value, and a minimum of the potential difference between the pair of communication lines is a negative voltage value that has a polarity opposite to the recessive threshold value of the first communication portion.

公开(公告)号：US09350422B2

公开(公告)日：2016-05-24

申请号：US14607200

申请日：2015-01-28

Applicant: DENSO CORPORATION

Inventor： Nobuaki Matsudaira ,  Shigeki Ohtsuka ,  Hironobu Akita

IPC: H04B3/00 ,  H04B3/54 ,  H04L29/08 ,  H04B1/10

CPC classification number: H04B3/54 ,  H04B1/10 ,  H04L67/1051

Abstract: A communication system includes multiple communication nodes and a communication line. The multiple communication nodes include a master and multiple slaves. The communication line cascade-connects the communication nodes and supplies electricity. The communication line corresponds to a feeder line. Each of the communication nodes is connected with the communication line through an inductor to be supplied with electricity. The each of the communication nodes is AC coupled to the communication line to transmit and receive a communication signal. The master and the slaves perform a bidirectional communication. A communication slave is provided. The communication slave is connected with a communication line through an inductor to be supplied with electricity. A communication master is provided.

Abstract translation: 通信系统包括多个通信节点和通信线路。 多个通信节点包括主站和多个从站。 通信线路级联连接通信节点并供电。 通信线对应于馈线。 每个通信节点通过电感器与通信线路连接以供电。 通信节点中的每一个被交流耦合到通信线路以发送和接收通信信号。 主机和从机进行双向通信。 提供通信从站。 通信从机通过电感器与通信线路连接以供电。 提供通信主机。

公开(公告)号：US09722819B2

公开(公告)日：2017-08-01

申请号：US15027534

申请日：2014-09-22

Applicant: DENSO CORPORATION

Inventor： Hironobu Akita ,  Shigeki Ohtsuka ,  Nobuaki Matsudaira ,  Takahisa Yoshimoto

IPC: H03H7/40 ,  H04L25/03 ,  H04B3/10 ,  H04L25/02 ,  H04B3/04 ,  H04B3/14

CPC classification number: H04L25/03057 ,  H04B3/04 ,  H04B3/10 ,  H04B3/14 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/03 ,  H04L2025/03815

Abstract: A distortion compensation system includes a first communication node including a first reception unit including an equalizer configured by a first digital filter unit and a first transmission unit including an emphasis circuit configured by a second digital filter unit, and a second communication node including a second transmission unit transmitting a training pattern before receiving normal data from the first communication node. The equalizer converges a filter constant of the first digital filter unit so that an error of the received training pattern is converged. The first transmission unit performs a distortion compensation using the converged filter constant of the first digital filter unit as at least a part of a filter constant of the second digital filter unit of the emphasis circuit, and then transmits the data.

公开(公告)号：US09276785B2

公开(公告)日：2016-03-01

申请号：US14807158

申请日：2015-07-23

Applicant: DENSO CORPORATION

Inventor： Nobuaki Matsudaira ,  Hironobu Akita ,  Shigeki Ohtsuka

IPC: H03H7/40 ,  H04L27/01 ,  H04B1/00 ,  H04L7/00

CPC classification number: H04L27/01 ,  H04B1/0003 ,  H04L7/0012 ,  H04L7/0025 ,  H04L7/0058 ,  H04L7/033 ,  H04L7/042

Abstract: A waveform equalization apparatus includes an A/D converter, a waveform equalizer, a training sequence generator, a clock recovery circuit, multiple matched filters, and a clock optimization logic. The A/D converter oversamples a reception signal in synchronization with a base clock signal and generates an A/D converted data sequence. The waveform equalizer performs an arithmetic operation to equalize a waveform. The training sequence generator generates a data sequence for training. The data sequence for training is used instead of an output data of the detector so as to converge a coefficient used in the arithmetic operation in advance. The clock recovery circuit supplies the base clock signal without executing a clock recovery operation during a training period, and executes the clock recovery operation according to the output data of the detector. The matched filters receive the A/D converted data sequence, and execute a filter arithmetic operation.

Abstract translation: 波形均衡装置包括A / D转换器，波形均衡器，训练序列发生器，时钟恢复电路，多个匹配滤波器和时钟优化逻辑。 A / D转换器与基本时钟信号同步地过采样接收信号，并产生A / D转换的数据序列。 波形均衡器进行算术运算以使波形均衡。 训练序列生成器生成用于训练的数据序列。 使用用于训练的数据序列代替检测器的输出数据，以便事先收敛在算术运算中使用的系数。 时钟恢复电路在训练期间提供基本时钟信号而不执行时钟恢复操作，并且根据检测器的输出数据执行时钟恢复操作。 匹配滤波器接收A / D转换的数据序列，并执行滤波算术运算。

公开(公告)号：US20140177739A1

公开(公告)日：2014-06-26

申请号：US14032224

申请日：2013-09-20

Applicant: Denso Corporation

Inventor： Nobuaki Matsudaira ,  Shigeki Ohtsuka ,  Hironobu Akita ,  Hirofumi Yamamoto

IPC: H04B3/30

CPC classification number: H04B3/30

Abstract: Nodes are connected in parallel between two transmission lines and configured to utilize a telecommunications standard of a differential transmission. At least one of the nodes includes two input/output terminals, a driver, a receiver, a resistor, and a comparator. The two input/output terminals are connected to the two transmission lines. The driver includes two output terminals connected to the two input/output terminals. The receiver includes two input terminals connected to the two input/output terminals. The resistor is connected between each of the two input/output terminals and one of a grand and a power supply voltage. The comparator compares a voltage between the transmission lines with a reference voltage to determine whether the transmission lines are in an idle state or in a communication state.

Abstract translation: 节点在两个传输线之间并联连接，并被配置为利用差分传输的电信标准。 节点中的至少一个包括两个输入/输出端子，一个驱动器，一个接收器，一个电阻器和一个比较器。 两个输入/输出端子连接到两条传输线。 驱动器包括连接到两个输入/输出端子的两个输出端子。 接收机包括连接到两个输入/输出端子的两个输入端子。 电阻器连接在两个输入/输出端子中的每一个之间，其中一个电源电压为高电平。 比较器将传输线之间的电压与参考电压进行比较，以确定传输线是处于空闲状态还是处于通信状态。