公开(公告)号：US20100309638A1

公开(公告)日：2010-12-09

申请号：US12783792

申请日：2010-05-20

申请人： Da-Jung Chen ,  Chi-Feng Huang ,  Yi-Tsung Chen ,  Huei-Ren You ,  Jeng-Jen Li

发明人： Da-Jung Chen ,  Chi-Feng Huang ,  Yi-Tsung Chen ,  Huei-Ren You ,  Jeng-Jen Li

IPC分类号： H05K7/02

CPC分类号： H01L23/49861 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012

摘要： An electronic element packaging module including a lead frame, an insulating layer and at least one electronic element is provided. The lead frame is a patterned metal sheet and has a first surface, a second surface opposite thereto and a through trench passing from the first surface to the second surface. A substrate portion and a plurality of lead portions around the substrate portion of the lead frame are defined by the through trench. The second surface of the lead frame is exposed outside the electronic element packaging module. The insulating layer disposed in the through trench has a third surface and a forth surface substantially coplanar with the first and the second surfaces, respectively. The electronic element disposed on the first surface is coupled to the lead frame.

摘要翻译： 提供了一种包括引线框架，绝缘层和至少一个电子元件的电子元件封装模块。 引线框架是图案化金属片，并且具有第一表面，与其相对的第二表面和从第一表面延伸到第二表面的通孔。 通过沟槽限定引线框架的基板部分周围的基板部分和多个引线部分。 引线框架的第二表面暴露在电子元件封装模块的外部。 布置在通孔中的绝缘层分别具有与第一表面和第二表面大致共面的第三表面和第四表面。 布置在第一表面上的电子元件连接到引线框架。

公开(公告)号：US08253041B2

公开(公告)日：2012-08-28

申请号：US12783792

申请日：2010-05-20

申请人： Da-Jung Chen ,  Chi-Feng Huang ,  Yi-Tsung Chen ,  Huei-Ren You ,  Jeng-Jen Li

发明人： Da-Jung Chen ,  Chi-Feng Huang ,  Yi-Tsung Chen ,  Huei-Ren You ,  Jeng-Jen Li

IPC分类号： H01L23/495

CPC分类号： H01L23/49861 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012

摘要： An electronic element packaging module including a lead frame, an insulating layer and at least one electronic element is provided. The lead frame is a patterned metal sheet and has a first surface, a second surface opposite thereto and a through trench passing from the first surface to the second surface. A substrate portion and a plurality of lead portions around the substrate portion of the lead frame are defined by the through trench. The second surface of the lead frame is exposed outside the electronic element packaging module. The insulating layer disposed in the through trench has a third surface and a forth surface substantially coplanar with the first and the second surfaces, respectively. The electronic element disposed on the first surface is coupled to the lead frame.

摘要翻译： 提供了一种包括引线框架，绝缘层和至少一个电子元件的电子元件封装模块。 引线框架是图案化金属片，并且具有第一表面，与其相对的第二表面和从第一表面延伸到第二表面的通孔。 通过沟槽限定引线框架的基板部分周围的基板部分和多个引线部分。 引线框架的第二表面暴露在电子元件封装模块的外部。 布置在通孔中的绝缘层分别具有与第一表面和第二表面大致共面的第三表面和第四表面。 布置在第一表面上的电子元件连接到引线框架。

公开(公告)号：US20080248194A1

公开(公告)日：2008-10-09

申请号：US11948320

申请日：2007-11-30

申请人： Akinobu NASU ,  Shyuan-Fang Chen ,  Wen-Jin Li ,  Yi-Tsung Chen

发明人： Akinobu NASU ,  Shyuan-Fang Chen ,  Wen-Jin Li ,  Yi-Tsung Chen

IPC分类号： B05D5/12

CPC分类号： H05K3/181 ,  C23C18/1651 ,  C23C18/1696 ,  C23C18/1841 ,  C23C18/30 ,  C23C18/40 ,  H05K3/244 ,  H05K2201/0344 ,  H05K2203/0716 ,  H05K2203/072

摘要： Methods and apparatus for producing a copper layer on substrate in a flat panel display manufacturing process, where the copper is electrodelessly deposited on a substrate to form a copper interconnection layer. A copper solution containing: CuSO4 5H2O as a copper source, potassium sodium tartrate or trisodium citrate as a complexing agent, glyoxylate, glyoxilic acid or sodium phosphate as a reducing agent, a sulfur organic compound as a stabilizing agent, and a pH adjusting agent, is used to form the copper interconnection layer on the substrate.

摘要翻译： 在平板显示器制造工艺中在基板上制造铜层的方法和装置，其中铜无电极沉积在基板上以形成铜互连层。 作为铜源的包含CuSO 4 H 2 O 2 O 2的铜溶液，作为络合剂的酒石酸钾钠盐或柠檬酸钠盐，乙醛酸盐，乙氧基化磷酸盐或磷酸钠作为还原剂 作为稳定剂的硫有机化合物和pH调节剂，用于在基板上形成铜互连层。

公开(公告)号：US20100317191A1

公开(公告)日：2010-12-16

申请号：US12066929

申请日：2007-03-15

申请人： Akinobu Nasu ,  Yi-Tsung Chen ,  Shyuan-Fang Chen

发明人： Akinobu Nasu ,  Yi-Tsung Chen ,  Shyuan-Fang Chen

IPC分类号： H01L21/768

CPC分类号： H01L27/124

摘要： A method of depositing a copper interconnection layer on a substrate for use in a flat panel display interconnection system, comprising the steps of: a) coating said substrate with a photoresist layer; b) patterning said photoresist layer to obtain a patterned photoresist substrate comprising at least one trench patterned into said photoresist layer; c) providing a first catalyzation layer onto the patterned photoresist substrate; d) providing an electroless plated layer of an insulation layer deposited onto said first catalyzation layer; e) removing the successively superimposed photoresist layer, catalyzation layer and insulation layer except in the at least one trench, to obtain a pattern of the first catalyzation layer with an insulation layer deposited thereon.

摘要翻译： 一种在用于平板显示器互连系统的衬底上沉积铜互连层的方法，包括以下步骤：a）用光致抗蚀剂层涂覆所述衬底; b）图案化所述光致抗蚀剂层以获得图案化的光致抗蚀剂基底，其包括图案化到所述光致抗蚀剂层中的至少一个沟槽; c）在图案化的光致抗蚀剂基底上提供第一催化层; d）提供沉积在所述第一催化层上的绝缘层的化学镀层; e）除去所述至少一个沟槽中的连续叠加的光致抗蚀剂层，催化层和绝缘层，以获得其上沉积有绝缘层的第一催化层的图案。

公开(公告)号：US20090004372A1

公开(公告)日：2009-01-01

申请号：US11995312

申请日：2005-07-13

申请人： Akinobu Nasu ,  Shyan-Fang Chen ,  Yi-Tsung Chen ,  Tsu-An Lin ,  Chiung-Sheng Hsiung

发明人： Akinobu Nasu ,  Shyan-Fang Chen ,  Yi-Tsung Chen ,  Tsu-An Lin ,  Chiung-Sheng Hsiung

IPC分类号： B05D5/12 ,  C09K19/52 ,  B32B17/06

CPC分类号： C23C18/50 ,  C23C18/1844 ,  C23C18/1893 ,  Y10T428/1095

摘要： Electroless NiWP layers are used for TFT Cu gate process. The NiWP deposition process comprises the following steps. (a) Cleaning of the base surface using for example UV light, ozone solution and/or alkaline mixture solution, (b) micro-etching of the base surface using, e.g. diluted acid, (c) catalyzation of the base surface using, e.g. SnCl 2 and PdCl 2 solutions, (d) conditioning of the base surface using reducing agent solution, and (e) NiWP deposition. It has been discovered that NiWP layers deposited under certain conditions could provide good adhesion to the glass substrate and to the Cu layer with a good Cu barrier capability. A NiWP layer in useful for adhesion, capping and/or barrier layers for TFT Cu gate process (e.g. for flat screen display panels).

摘要翻译： 无电镀NiWP层用于TFT Cu栅极工艺。 NiWP沉积工艺包括以下步骤。 （a）使用例如UV光，臭氧溶液和/或碱性混合物溶液清洗基底表面，（b）使用例如紫外光， 稀释的酸，（c）基底表面的催化。 SnCl 2和PdCl 2溶液，（d）使用还原剂溶液调节基底表面，和（e）NiWP沉积。 已经发现，在某些条件下沉积的NiWP层可以对玻璃基底和具有良好Cu阻挡能力的Cu层提供良好的粘附性。 用于TFT Cu栅极工艺（例如用于平板显示面板）的粘合，封盖和/或阻挡层的NiWP层。