公开(公告)号：US20090004372A1

公开(公告)日：2009-01-01

申请号：US11995312

申请日：2005-07-13

申请人： Akinobu Nasu ,  Shyan-Fang Chen ,  Yi-Tsung Chen ,  Tsu-An Lin ,  Chiung-Sheng Hsiung

发明人： Akinobu Nasu ,  Shyan-Fang Chen ,  Yi-Tsung Chen ,  Tsu-An Lin ,  Chiung-Sheng Hsiung

IPC分类号： B05D5/12 ,  C09K19/52 ,  B32B17/06

CPC分类号： C23C18/50 ,  C23C18/1844 ,  C23C18/1893 ,  Y10T428/1095

摘要： Electroless NiWP layers are used for TFT Cu gate process. The NiWP deposition process comprises the following steps. (a) Cleaning of the base surface using for example UV light, ozone solution and/or alkaline mixture solution, (b) micro-etching of the base surface using, e.g. diluted acid, (c) catalyzation of the base surface using, e.g. SnCl 2 and PdCl 2 solutions, (d) conditioning of the base surface using reducing agent solution, and (e) NiWP deposition. It has been discovered that NiWP layers deposited under certain conditions could provide good adhesion to the glass substrate and to the Cu layer with a good Cu barrier capability. A NiWP layer in useful for adhesion, capping and/or barrier layers for TFT Cu gate process (e.g. for flat screen display panels).

摘要翻译： 无电镀NiWP层用于TFT Cu栅极工艺。 NiWP沉积工艺包括以下步骤。 （a）使用例如UV光，臭氧溶液和/或碱性混合物溶液清洗基底表面，（b）使用例如紫外光， 稀释的酸，（c）基底表面的催化。 SnCl 2和PdCl 2溶液，（d）使用还原剂溶液调节基底表面，和（e）NiWP沉积。 已经发现，在某些条件下沉积的NiWP层可以对玻璃基底和具有良好Cu阻挡能力的Cu层提供良好的粘附性。 用于TFT Cu栅极工艺（例如用于平板显示面板）的粘合，封盖和/或阻挡层的NiWP层。

公开(公告)号：US06197698B1

公开(公告)日：2001-03-06

申请号：US09340400

申请日：1999-06-28

申请人： Jui-Tsen Huang ,  Kuang-Hua Shih ,  Tsu-An Lin ,  Chan-Lon Yang

发明人： Jui-Tsen Huang ,  Kuang-Hua Shih ,  Tsu-An Lin ,  Chan-Lon Yang

IPC分类号： H01L213065

CPC分类号： H01L21/32139 ,  H01L21/28035 ,  H01L21/32137 ,  H01L21/823437

摘要： The present invention provides a method for etching a poly-silicon layer of a semiconductor wafer. The semiconductor wafer comprises a dielectric layer, a poly-silicon layer situated on the dielectric layer and containing dopants to a predetermined depth, and a photo-resist layer having a rectangular cross-section above a predetermined area of the poly-silicon layer. The semiconductor wafer is processed in a plasma chamber. A first dry-etching process is performed to vertically etch away the dopant-containing portion of the poly-silicon layer not covered by the photo-resist layer. Then, a second dry-etching process is performed to vertically etch away the residual portion of the poly-silicon layer not covered by the photo-resist layer down to the surface of the dielectric layer. The etching gases used in the first dry-etching process differ from those used in the second dry-etching process, and the main etching gas of the first dry-etching process is C2F6.

摘要翻译： 本发明提供一种蚀刻半导体晶片的多晶硅层的方法。 半导体晶片包括电介质层，位于电介质层上的多晶硅层，并且含有预定深度的掺杂剂，以及在多晶硅层的预定区域之上具有矩形横截面的光致抗蚀剂层。 半导体晶片在等离子体室中进行处理。 执行第一干蚀刻工艺以垂直蚀刻掉未被光致抗蚀剂层覆盖的多晶硅层的含掺杂物部分。 然后，进行第二干法蚀刻工艺，以将未被光刻胶层覆盖的多晶硅层的剩余部分垂直蚀刻掉到电介质层的表面。 在第一干蚀刻工艺中使用的蚀刻气体与第二干蚀刻工艺中使用的蚀刻气体不同，第一干法蚀刻工艺的主蚀刻气体为C2F6。

公开(公告)号：US5923989A

公开(公告)日：1999-07-13

申请号：US81598

申请日：1998-05-20

申请人： Shian-Jyh Lin ,  Tsu-An Lin ,  Wen-Chieh Chang ,  Shiou-Yu Wang ,  Tean-Sen Jen ,  Hui-Jen Yang ,  Jia-Shyong Cheng ,  Ming-Teng Hsieh

发明人： Shian-Jyh Lin ,  Tsu-An Lin ,  Wen-Chieh Chang ,  Shiou-Yu Wang ,  Tean-Sen Jen ,  Hui-Jen Yang ,  Jia-Shyong Cheng ,  Ming-Teng Hsieh

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/84

摘要： A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers. Next, the polysilicon layer is anisotropically etched by using the rugged polysilicon layer as an etching mask to transfer rugged surface profile from the rugged polysilicon layer to the polysilicon layer. Finally, an interelectrode dielectric layer and a third polysilicon layer as top electrodes of the capacitors are sequentially formed to complete the rugged capacitor for high density DRAM applications.

摘要翻译： 公开了一种制造高密度动态随机存取存储器（DRAM）单元的坚固电容器结构的方法。 首先，在半导体硅衬底上形成MOSFET，字线和位线。 接下来，在整个硅衬底上依次沉积介电层和掺杂多晶硅层。 然后将电介质层和掺杂多晶硅层部分地蚀刻到开源接触窗口。 然后，沉积覆盖掺杂多晶硅层并填充到源极接触窗口中的多晶硅层。 接下来，部分蚀刻多晶硅层和掺杂多晶硅层以限定电容器的底部电极。 接下来，进行倾斜角注入以将杂质植入多晶硅层的顶表面和四个侧壁以及掺杂多晶硅层。 接下来，沉积覆盖多晶硅，掺杂多晶硅和第三介电层的坚固的多晶硅层。 接下来，通过使用坚固的多晶硅层作为蚀刻掩模来将多晶硅层各向异性地蚀刻，以将粗糙的表面轮廓从坚固的多晶硅层转移到多晶硅层。 最后，依次形成作为电容器顶电极的电极间电介质层和第三多晶硅层，以完成用于高密度DRAM应用的坚固电容器。

公开(公告)号：US06180532B2

公开(公告)日：2001-01-30

申请号：US09213129

申请日：1998-12-15

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

IPC分类号： H01L213065

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144

摘要： A method for forming a contact hole in a silicon oxide layer formed over a silicon nitride layer and a substrate performs an etching process with an etchant, C4F8/Ar or C4F8/C2F6/Ar, on an inductively coupled plasma etcher. The inductively coupled plasma etcher contains a chamber, a ring, and a roof. The etchant used in the etching process is controlled by conditions that include a C4F8 flow of about 10 to 20 sccm, a CO flow of less than about 100 sccm, and an Ar flow of about 50 to 500 sccm. In the meantime, the conditions of the inductively coupled plasma etcher include a roof temperature of about 150 to 300 ° C., a ring temperature of about 150 to 400 ° C., and a pressure within the chamber of about 4 to 50 mtorr. By performing a plasma etching process under the foregoing conditions, a properly profiled contact hole is obtained.

摘要翻译： 在形成在氮化硅层和基板上的氧化硅层中形成接触孔的方法在电感耦合等离子体蚀刻器上用蚀刻剂C4F8 / Ar或C4F8 / C2F6 / Ar进行蚀刻处理。 电感耦合等离子体蚀刻器包含一个室，一个环和一个屋顶。 在蚀刻工艺中使用的蚀刻剂由包括约10至20sccm的C 4 F 8流量，小于约100sccm的CO流量和约50至500sccm的Ar流量的条件控制。 同时，电感耦合等离子体蚀刻器的条件包括约150-300℃的屋顶温度，约150-400℃的环境温度和室内压力为约4-50mtorr。 通过在上述条件下进行等离子体蚀刻工艺，可以获得适当的异型接触孔。

公开(公告)号：US6066541A

公开(公告)日：2000-05-23

申请号：US66566

申请日：1998-04-27

申请人： Ming-Teng Hsieh ,  Tsu-An Lin ,  Pei-Ying Lee ,  Hsing-Chuan Tsai

发明人： Ming-Teng Hsieh ,  Tsu-An Lin ,  Pei-Ying Lee ,  Hsing-Chuan Tsai

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/82

摘要： A method for fabricating a cylindrical capacitor is provided. This invention uses a composite structure composed of stacked barrier/scarificing/mask layers to prevent the contact plug of the capacitor from being attacked by wet etchants. An insulating layer is formed over a substrate having a source region, a drain region, and a gate electrode. Then a barrier layer, a sacrificing layer and a mask layer are sequentially formed over the insulating layer. Next, a contact hole is formed over the source region and spacers are formed on the sidewalls of the contact hole. After a storage electrode of the capacitor is formed and exposed portions of the mask layer are removed, the sacrificing layer is isotropically etched using the spacers and the barrier layer as stopping layers. Thereafter, a capacitor dielectric layer and an opposite electrode are formed over the storage electrode thereby completing the capacitor.

摘要翻译： 提供一种制造圆柱形电容器的方法。 本发明使用由堆叠的阻挡/清除/掩模层组成的复合结构，以防止电容器的接触塞被湿蚀刻剂侵蚀。 在具有源极区域，漏极区域和栅极电极的衬底上形成绝缘层。 然后在绝缘层上依次形成阻挡层，牺牲层和掩模层。 接下来，在源极区域上形成接触孔，并且在接触孔的侧壁上形成间隔物。 在形成电容器的存储电极并且去除掩模层的暴露部分之后，使用间隔物和阻挡层作为停止层进行各向同性蚀刻。 此后，在存储电极上形成电容器电介质层和相对电极，从而完成电容器。

公开(公告)号：US06277736B1

公开(公告)日：2001-08-21

申请号：US09206884

申请日：1998-12-08

申请人： L. Y. Chen ,  Heinz Shih ,  Wen-Yi Hsieh ,  Tsu-An Lin

发明人： L. Y. Chen ,  Heinz Shih ,  Wen-Yi Hsieh ,  Tsu-An Lin

IPC分类号： H01L2144

CPC分类号： H01L21/32137 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32136

摘要： A method for forming a gate. A gate oxide layer, a polysilicon layer and a barrier layer are subsequently formed on a substrate, on which an isolation structure is formed. A conductive layer is formed on the barrier layer by sputtering deposition using titanium silicide with a low silicon content as a target. A rapid thermal process (RTP) is performed to remove the polymer nodule formed by sputtering deposition. An anti-reflection layer is formed on the conductive layer. The anti-reflection layer, the conductive layer and the barrier layer are patterned by the etchant composed of chlorine/nitrogen/hexafluoroethane until the polysilicon layer is exposed. Using the anti-reflection layer, the conductive layer and the barrier layer as a mask, the exposed polysilicon layer and the gate oxide layer underlying the exposed polysilicon layer are removed by the etchant composed of chlorine/hydrogen bromide/helium/oxygen until the substrate is exposed and a gate is formed.

摘要翻译： 一种形成栅极的方法。 随后在其上形成有隔离结构的基板上形成栅极氧化物层，多晶硅层和势垒层。 通过使用具有低硅含量的硅化钛作为靶的溅射沉积在阻挡层上形成导电层。 进行快速热处理（RTP）以除去由溅射沉积形成的聚合物结节。 在导电层上形成防反射层。 通过由氯/氮/六氟乙烷组成的蚀刻剂将抗反射层，导电层和阻挡层图案化，直到多晶硅层露出。 使用防反射层，导电层和阻挡层作为掩模，暴露的多晶硅层和暴露的多晶硅层下面的栅极氧化物层被由氯/溴化氢/氦/氧组成的蚀刻剂除去直到基板 被暴露并形成门。

公开(公告)号：US5994233A

公开(公告)日：1999-11-30

申请号：US172507

申请日：1998-10-14

申请人： Tong-Yu Chen ,  Chan-Lon Yang ,  Tsu-An Lin

发明人： Tong-Yu Chen ,  Chan-Lon Yang ,  Tsu-An Lin

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/3065

CPC分类号： H01L21/31116

摘要： An oxide etching method using low-medium density plasma includes a first etching step to pre-etch the oxide layer with low etching selectivity etchant to pre-form a contact opening and a monitoring opening. The low etching selectivity etchant can also etch the photoresist layer and the photoresist reaction residue. Then, a second etching with high etching selectivity on the oxide is performed to completely form the contact opening with a SAC property and the monitoring opening. The openings expose the substrate.

摘要翻译： 使用低介质密度等离子体的氧化物蚀刻方法包括用低蚀刻选择性蚀刻剂预蚀刻氧化物层以预先形成接触开口和监测开口的第一蚀刻步骤。 低蚀刻选择性蚀刻剂也可以蚀刻光致抗蚀剂层和光致抗蚀剂反应残余物。 然后，执行对氧化物具有高蚀刻选择性的第二蚀刻，以完全形成具有SAC特性和监测开口的接触开口。 开口露出基板。

公开(公告)号：US06380082B2

公开(公告)日：2002-04-30

申请号：US09250631

申请日：1999-02-16

申请人： Chih-Ming Huang ,  Tsu-An Lin

发明人： Chih-Ming Huang ,  Tsu-An Lin

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/76808 ,  H01L21/76843

摘要： An improved method of preventing copper poisoning in the fabrication of metal interconnects on a semiconductor substrate comprises sequential formation of a copper layer, a first stop layer, a first inter-metal dielectric layer, a second stop layer, and a second inter-metal dielectric layer over the substrate. The second inter-metal dielectric layer and the second stop layer are defined to form an opening. A conformal first glue/barrier layer is formed over the substrate. The first glue/barrier layer and the first inter-metal dielectric layer are patterned to form a via hole below the opening until the first stop layer is exposed. Spacers are formed on sidewalls of the opening and the via hole below the opening. The first stop layer at bottom of the via hole is removed to expose the copper layer.

摘要翻译： 在半导体衬底的金属互连制造中防止铜中毒的改进方法包括顺序地形成铜层，第一阻挡层，第一金属间介电层，第二阻挡层和第二金属间电介质 层。 第二金属间介电层和第二阻挡层被限定为形成开口。 在衬底上形成共形的第一胶/阻挡层。 将第一胶/阻挡层和第一金属间介电层图案化以在开口下方形成通孔，直到暴露第一​​停止层。 间隔件形成在开口的侧壁和开口下方的通孔中。 去除通孔底部的第一停止层以露出铜层。

公开(公告)号：US6150223A

公开(公告)日：2000-11-21

申请号：US287881

申请日：1999-04-07

申请人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

发明人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

IPC分类号： H01L21/60 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76

CPC分类号： H01L21/76897 ,  H01L21/823468

摘要： A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate. Removing the first photoresist layer and the fourth dielectric layer of the interior circuit, a fifth dielectric layer is formed on the third dielectric layer of the interior circuit. The fourth dielectric layer and the top surface of the second dielectric layer of the peripheral circuit are removed. The fifth dielectric layer is formed on the first dielectric layer and the third peripheral of the peripheral circuit, and then the second photoresist layer on the fifth dielectric layer, wherein the third photoresist layer is patterned as a bit-line contact via of the interior circuit and the bit-line contact vias of the peripheral circuit. Finally, anisotropically etching the third photoresist layer and the fifth dielectric layer, a bit-line to the substrate contact via and a bit-line to the gate contact via are formed inside the fifth dielectric layer.

摘要翻译： 公开了一种用于形成不同宽度的栅极间隔物的方法。 该方法包括首先在半导体衬底上形成栅氧化层。 在栅极氧化物层上依次形成多晶硅层，导电层，第一介电层。 使用它们作为内部栅极和外围栅极进一步蚀刻第一介电层，导电层，多晶硅层和栅极氧化物层。 接下来，在内部栅极和外围栅极上形成第二电介质层，第三电介质层和第四电介质层，并且第一光致抗蚀剂层邻接内部电路的第四电介质层的表面。 此外，蚀刻外围栅极的第四介电层以形成外围栅极的第二间隔物，并且蚀刻外围栅极的第三介电层以形成外围栅极的第一间隔物。 去除内部电路的第一光致抗蚀剂层和第四电介质层，在内部电路的第三电介质层上形成第五电介质层。 除去第四电介质层和外围电路的第二电介质层的顶表面。 第五电介质层形成在第一电介质层和外围电路的第三外围，然后形成在第五介电层上的第二光致抗蚀剂层，其中第三光致抗蚀剂层被图案化为内部电路的位线接触通孔 和外围电路的位线接触通孔。 最后，在第五介电层内形成各向异性蚀刻第三光致抗蚀剂层和第五电介质层，到基板接触通孔的位线和到栅极接触通孔的位线。