公开(公告)号：US06542406B2

公开(公告)日：2003-04-01

申请号：US09905612

申请日：2001-07-13

申请人： Dae-Seok Byeon ,  Myung-Jae Kim ,  Young-Ho Lim ,  Seung-Keun Lee

发明人： Dae-Seok Byeon ,  Myung-Jae Kim ,  Young-Ho Lim ,  Seung-Keun Lee

IPC分类号： G11C1604

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C16/08

摘要： A nonvolatile semiconductor memory device includes a plurality of first wordlines, a plurality of second wordlines coupled to memory cells, the second wordlines being assigned to each of memory sectors, a plurality of transistors each of which connects a first wordline to a second wordline, and a circuit for controlling the transistors in common. One of the first wordlines is connected to one of the second wordlines through one of the transistors. A circuit area for decoding is reduced and current consumption is minimized.

公开(公告)号：US07852682B2

公开(公告)日：2010-12-14

申请号：US11830260

申请日：2007-07-30

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.

摘要翻译： 闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。 一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。 局部电压低于通过电压，等于或高于接地电压。 在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

公开(公告)号：US07529134B2

公开(公告)日：2009-05-05

申请号：US11439797

申请日：2006-05-24

申请人： Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

发明人： Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202

摘要： A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells.

摘要翻译： 包括多个存储器单元的非易失性存储器件的编程方法包括提供具有与其相关联的相应多个编程电压的多个程序循环。 多个程序循环中的第一个被激活以产生第一编程电压以编程多个存储器单元中的第一个。 多个程序循环中的第二个程序循环被激活以产生第二编程电压以编程多个存储器单元中的第二个。

公开(公告)号：US20080123417A1

公开(公告)日：2008-05-29

申请号：US11605227

申请日：2006-11-29

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G05F1/10 ,  G11C8/10

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  H02M3/07

摘要： A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.

公开(公告)号：US20050270882A1

公开(公告)日：2005-12-08

申请号：US10915294

申请日：2004-08-10

申请人： Wook-Ghee Han ,  Dae-Seok Byeon ,  Sung-Soo Lee ,  Young-Ho Lim

发明人： Wook-Ghee Han ,  Dae-Seok Byeon ,  Sung-Soo Lee ,  Young-Ho Lim

IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/30

CPC分类号： G11C16/12 ,  G11C5/145

摘要： High voltage generators include a charge pump and a ripple reduction circuit that includes an integrated discharge path. The ripple reduction circuit limits the voltage level from a charge pump when the charge pump is in a first operating mode and provides a discharge path that from the output terminal of the ripple reduction circuit to the output of the charge pump when the charge pump is in a second operating mode. Semiconductor memories incorporating such high voltage generators are also provided. Coupling circuits having an integrated discharge path are also provided.

摘要翻译： 高压发生器包括电荷泵和包括集成放电路径的纹波降低电路。 当电荷泵处于第一操作模式时，纹波降低电路限制来自电荷泵的电压电平，并且当电荷泵处于第一操作模式时提供从脉动降低电路的输出端子到电荷泵的输出的放电路径 第二种操作模式。 还提供了包括这种高电压发生器的半导体存储器。 还提供具有集成放电路径的耦合电路。

公开(公告)号：US08045380B2

公开(公告)日：2011-10-25

申请号：US12939251

申请日：2010-11-04

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.

摘要翻译： 闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。 一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。 局部电压低于通过电压，等于或高于接地电压。 在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

公开(公告)号：US07974125B2

公开(公告)日：2011-07-05

申请号：US12822246

申请日：2010-06-24

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

摘要翻译： 闪速存储器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，被配置为响应于块地址产生块选择信号并且产生标志信号的控制器， 块地址对应于坏块，并且输出缓冲器被配置为响应于指示块地址对应于坏块的标志信号输出固定数据。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

公开(公告)号：US07151702B2

公开(公告)日：2006-12-19

申请号：US10915294

申请日：2004-08-10

申请人： Wook-Ghee Han ,  Dae-Seok Byeon ,  Sung-Soo Lee ,  Young-Ho Lim

发明人： Wook-Ghee Han ,  Dae-Seok Byeon ,  Sung-Soo Lee ,  Young-Ho Lim

IPC分类号： G11C5/14

CPC分类号： G11C16/12 ,  G11C5/145

摘要： High voltage generators include a charge pump and a ripple reduction circuit that includes an integrated discharge path. The ripple reduction circuit limits the voltage level from a charge pump when the charge pump is in a first operating mode and provides a discharge path that from the output terminal of the ripple reduction circuit to the output of the charge pump when the charge pump is in a second operating mode. Semiconductor memories incorporating such high voltage generators are also provided. Coupling circuits having an integrated discharge path are also provided.

摘要翻译： 高压发生器包括电荷泵和包括集成放电路径的纹波降低电路。 当电荷泵处于第一操作模式时，纹波降低电路限制来自电荷泵的电压电平，并且当电荷泵处于第一操作模式时提供从脉动降低电路的输出端子到电荷泵的输出的放电路径 第二种操作模式。 还提供了包括这种高电压发生器的半导体存储器。 还提供具有集成放电路径的耦合电路。

公开(公告)号：US20060279999A1

公开(公告)日：2006-12-14

申请号：US11381556

申请日：2006-05-04

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/16

摘要： Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.

摘要翻译： 提供擦除闪速存储器件中的数据的方法，其中产生多个字线偏置电压，其包括具有至少两个不同电平的字线偏置电压，通过将不同的字线偏置电压施加到多个字线中的相应字线来擦除数据 同时将擦除电压施加到存储器单元的主体区域，以及验证存储器单元的擦除状态。 根据这些方法，可能会降低可能由存储器单元之间的擦除耦合比的偏差导致的阈值 - 电压分布曲线的扩展。

公开(公告)号：US06717857B2

公开(公告)日：2004-04-06

申请号：US10279386

申请日：2002-10-23

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C1134

CPC分类号： G11C16/10 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C16/26 ,  G11C2216/14

摘要： A non-volatile memory device according to embodiments of the invention includes a page buffer acting as a sense amplifier during a read operation and as a write driver during a program operation. The page buffer has two sense and latch blocks, which exclusively carry out the same function. While one of the sense and latch blocks carries out a read operation, the other sense and latch block outputs previously sensed data to the exterior. Further, while one of the sense and latch blocks carries out a program operation, the other sense and latch block loads data to be programmed. Due to the page buffer, an operation speed of the non-volatile memory device can be enhanced.

摘要翻译： 根据本发明的实施例的非易失性存储器件包括在读取操作期间用作读出放大器的页缓冲器，以及在编程操作期间作为写驱动器。 页面缓冲区具有两个感测和锁存块，它们独有地执行相同的功能。 虽然其中一个感测和锁存块执行读取操作，但另一个感测和锁存块将先前感测的数据输出到外部。 此外，当感测和锁存块中的一个执行编程操作时，另一个感测和锁存块加载待编程的数据。 由于页面缓冲器，可以提高非易失性存储器件的操作速度。