公开(公告)号：US07529134B2

公开(公告)日：2009-05-05

申请号：US11439797

申请日：2006-05-24

申请人： Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

发明人： Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202

摘要： A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells.

摘要翻译： 包括多个存储器单元的非易失性存储器件的编程方法包括提供具有与其相关联的相应多个编程电压的多个程序循环。 多个程序循环中的第一个被激活以产生第一编程电压以编程多个存储器单元中的第一个。 多个程序循环中的第二个程序循环被激活以产生第二编程电压以编程多个存储器单元中的第二个。

公开(公告)号：US20070074194A1

公开(公告)日：2007-03-29

申请号：US11439797

申请日：2006-05-24

申请人： Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

发明人： Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

IPC分类号： G06F9/45

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202

摘要： A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells. Related devices are also discussed.

摘要翻译： 包括多个存储器单元的非易失性存储器件的编程方法包括提供具有与其相关联的相应多个编程电压的多个程序循环。 多个程序循环中的第一个被激活以产生第一编程电压以编程多个存储器单元中的第一个。 多个程序循环中的第二个程序循环被激活以产生第二编程电压以编程多个存储器单元中的第二个。 还讨论了相关设备。

公开(公告)号：US07505350B2

公开(公告)日：2009-03-17

申请号：US11642105

申请日：2006-12-20

申请人： Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

发明人： Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

IPC分类号： G11C17/18

CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C16/04 ,  G11C17/18 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.

摘要翻译： 用于半导体存储器件的电压调节器的控制电路包括选件熔丝电路和定影控制电路。 选项熔丝电路包括多个保险丝和选择电路，其根据控制信号选择多个保险丝之一。 响应于所选择的多个保险丝的状态来调整与电​​压复位电路相关联的输出电压。 熔断控制电路产生控制信号以允许电压复位电路对输出电压进行多次调节。 选项保险丝电路可以是多个选项保险丝电路，并且可以响应于选项保险丝电路的多个保险丝中的相应选择的保险丝的状态来调整输出电压。

公开(公告)号：US07110292B2

公开(公告)日：2006-09-19

申请号：US11020517

申请日：2004-12-22

申请人： Wook-Ghee Hahn ,  Sung-Soo Lee ,  Dae-Seok Byeon

发明人： Wook-Ghee Hahn ,  Sung-Soo Lee ,  Dae-Seok Byeon

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C8/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5641

摘要： A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.

公开(公告)号：US07405978B2

公开(公告)日：2008-07-29

申请号：US11513157

申请日：2006-08-31

申请人： Wook-Ghee Hahn ,  Dae Seok Byeon

发明人： Wook-Ghee Hahn ,  Dae Seok Byeon

IPC分类号： G11C16/24

CPC分类号： G11C5/063 ,  G11C16/24

摘要： A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A common source line is formed in a common source layer and adapted to provide a predetermined source voltage to the plurality of memory cells. A voltage control block comprising a plurality of voltage control circuits adapted to control the voltage levels of the plurality of bitlines through voltage supply lines formed in a voltage-line metal layer is formed on one side of the cell array.

摘要翻译： 半导体存储器件包括包括多个存储单元的单元阵列。 半导体存储器件还包括形成在位层中并连接到多个存储器单元的多个位线，其中位线沿着单个方向从单元阵列延伸。 公共源极线形成在公共源层中并且适于向多个存储器单元提供预定的源极电压。 电压控制块包括多个电压控制电路，其适于通过形成在电压线金属层中的电压供给线来控制多个位线的电压电平，该电压控制电路形成在电池阵列的一侧。

公开(公告)号：US07215181B2

公开(公告)日：2007-05-08

申请号：US11025765

申请日：2004-12-28

申请人： Wook-Ghee Hahn ,  Dae-Seok Byeon

发明人： Wook-Ghee Hahn ,  Dae-Seok Byeon

IPC分类号： G05F1/10 ,  H03L7/00

CPC分类号： H02M3/07 ,  H02M1/14

摘要： The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.

摘要翻译： 本文公开的本发明是高压发生器电路。 高压发生器电路包括电荷泵和泵时钟信号发生器。 当高电压低于目标电压时，泵时钟信号被选通到电荷泵。 高电压达到目标电压后，高压周期性下降到目标电压以下。 在高电压达到目标电压之后，泵时钟发生器电路限制泵时钟信号的传输，从而每个周期只有N个时钟信号被选通到电荷泵，其中N是一个或更多个。

公开(公告)号：US20070183245A1

公开(公告)日：2007-08-09

申请号：US11642105

申请日：2006-12-20

申请人： Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

发明人： Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

IPC分类号： G11C17/18

CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C16/04 ,  G11C17/18 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.

摘要翻译： 用于半导体存储器件的电压调节器的控制电路包括选件熔丝电路和定影控制电路。 选项熔丝电路包括多个保险丝和选择电路，其根据控制信号选择多个保险丝之一。 响应于所选择的多个保险丝的状态来调整与电​​压复位电路相关联的输出电压。 熔断控制电路产生控制信号以允许电压复位电路对输出电压进行多次调节。 选项保险丝电路可以是多个选项保险丝电路，并且可以响应于选项保险丝电路的多个保险丝中的相应选择的保险丝的状态来调整输出电压。

公开(公告)号：US20060061411A1

公开(公告)日：2006-03-23

申请号：US11025765

申请日：2004-12-28

申请人： Wook-Ghee Hahn ,  Dae-Seok Byeon

发明人： Wook-Ghee Hahn ,  Dae-Seok Byeon

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M1/14

摘要： The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.

摘要翻译： 本文公开的本发明是高压发生器电路。 高压发生器电路包括电荷泵和泵时钟信号发生器。 当高电压低于目标电压时，泵时钟信号被选通到电荷泵。 高电压达到目标电压后，高压周期性下降到目标电压以下。 在高电压达到目标电压之后，泵时钟发生器电路限制泵时钟信号的传输，从而每个周期只有N个时钟信号被选通到电荷泵，其中N是一个或更多个。

公开(公告)号：US20060044923A1

公开(公告)日：2006-03-02

申请号：US11020517

申请日：2004-12-22

申请人： Wook-Ghee Hahn ,  Sung-Soo Lee ,  Dae-Seok Byeon

发明人： Wook-Ghee Hahn ,  Sung-Soo Lee ,  Dae-Seok Byeon

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5641

摘要： A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.

摘要翻译： 非易失性存储器件包括非易失性存储器单元，其相应​​的一个被配置为以单位模式存储单个位，并且以多位模式存储多个位。 单个分压器被配置为以单比特模式在非易失性存储器单元中产生至少第一编程电压，并且生成与第一编程电压不同的至少第二编程电压， 多位模式下的易失性存储单元。

公开(公告)号：US20070182398A1

公开(公告)日：2007-08-09

申请号：US11698945

申请日：2007-01-29

申请人： Wook-Ghee Hahn

发明人： Wook-Ghee Hahn

IPC分类号： G05F1/00

CPC分类号： G05F1/56

摘要： Provided is a voltage regulator. The voltage regulator includes a level down shifter reducing an applied high voltage, a voltage divider dividing the reduced high voltage to generate a first division result, a comparator comparing a reference voltage to the first division result, and a driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider. The voltage divider divides the output voltage to generate a second division result serving as a voltage control signal fed back to the level down shifter.

摘要翻译： 提供电压调节器。 电压调节器包括降低施加的高电压的电平降低移位器，分压降低的高电压以产生第一分割结果的分压器，将参考电压与第一分频结果进行比较的比较器，以及产生基于 比较结果，并提供输出电压分压器。 分压器分压输出电压以产生用作反馈到电平降低变换器的电压控制信号的第二分频结果。