公开(公告)号：USRE36993E

公开(公告)日：2000-12-19

申请号：US612443

申请日：1996-03-07

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10805

摘要： A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.

摘要翻译： 动态随机存取存储器件包括半导体衬底，衬底上的多个平行字线以及与衬底上的字线横向的多对位线。 在字线和位线之间限定的交叉点选择性地布置单晶体管存储单元的阵列。 该阵列被细分成多个子阵列部分。 感测放大器部分连接到位线。 读出放大器部分包括第一和第二读出放大器电路。 位线的相邻位线对包括第一位线对和第二位线对，其中一个具有折叠位线布置，其包括在要连接到第一读出放大器电路的某个子阵列部分中 并且另一个具有延伸到子阵列部分和与其相邻的另一个子阵列部分的开放位线布置，并且连接到第二读出放大器电路。

公开(公告)号：US5555519A

公开(公告)日：1996-09-10

申请号：US348068

申请日：1994-11-23

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10805

摘要： A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.

公开(公告)号：US5838038A

公开(公告)日：1998-11-17

申请号：US478620

申请日：1995-06-07

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

IPC分类号： G11C7/18 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C2211/4013

摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.

摘要翻译： 半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极 其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽 配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极 另一个源极和漏极到存储电极。

公开(公告)号：US5732010A

公开(公告)日：1998-03-24

申请号：US771434

申请日：1996-12-20

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe

IPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/401

CPC分类号： H01L27/10805 ,  G11C11/4097 ,  G11C7/18

摘要： A semiconductor memory device of the present invention comprises a plurality of word lines formed on a substrate, a plurality of bit lines perpendicular to the word lines and divided into bit-line groups in the column direction along the word line, each group containing three bit lines, and arrays of memory cells arranged at the intersections of word lines and bit lines, wherein two memory cells are placed at two of every three adjacent intersections arranged in each of the row and column directions, and where these memory cell arrays are divided into subarrays in the row direction, each of the cell arrays is divided into cell blocks in the row direction, two of the three bit lines in each bit-line group along the bit line are crossed each other between adjacent cell blocks, and a plurality of sense amplifiers are placed between adjacent cell arrays so as to correspond to cell blocks.

摘要翻译： 本发明的半导体存储器件包括形成在基板上的多条字线，与字线垂直的多个位线，沿着字线在列方向上分成位线组，每组包含三位 线和排列在字线和位线的交点处的存储器单元阵列，其中两个存储单元被放置在布置在行和列方向中的每一个中的每三个相邻交点中的两个处，并且其中这些存储单元阵列被分成 在行方向上的子阵列中，每个单元阵列被划分为行方向上的单元块，沿位线的每个位线组中的三个位线中的两个在相邻单元块之间彼此交叉，并且多个 感测放大器被放置在相邻单元阵列之间，以便对应于单元块。

公开(公告)号：US5396450A

公开(公告)日：1995-03-07

申请号：US123466

申请日：1993-09-20

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10805

摘要： A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.

公开(公告)号：US08792266B2

公开(公告)日：2014-07-29

申请号：US13605674

申请日：2012-09-06

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： A memory cell is formed with a resistance variable element, which is interposed between first and second electrodes and can store resistance changes representing 2 or more different values, and first and second cell transistors having source terminals thereof connected to the first electrode, and gates thereof to a word line. A drain of the first cell transistor is connected to a bit line, and a drain of the second cell transistor is connected to a data line. The second electrode is connected to a source line. During a read operation, the first and second cell transistors are kept in an ON state, and a current is supplied from the bit line to the source line through the memory cell. Data is read according to the electrical potential difference between the data line and the source line.

摘要翻译： 存储单元形成有电阻可变元件，其被插入在第一和第二电极之间，并且可以存储表示2个或更多个不同值的电阻变化，以及其源极端子连接到第一电极的第一和第二单元晶体管及其栅极 到一个字线。 第一单元晶体管的漏极连接到位线，并且第二单元晶体管的漏极连接到数据线。 第二电极连接到源极线。 在读取操作期间，第一和第二单元晶体管保持在导通状态，并且通过存储单元从位线向源极线提供电流。 根据数据线和源极线之间的电位差读取数据。

公开(公告)号：US08650373B2

公开(公告)日：2014-02-11

申请号：US12860160

申请日：2010-08-20

申请人： Kosuke Hatsuda ,  Daisaburo Takashima

发明人： Kosuke Hatsuda ,  Daisaburo Takashima

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F11/1441

摘要： According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n≧2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data.

摘要翻译： 根据一个实施例，存储器系统包括非易失性第一存储器，非易失性第二存储器，数据复制处理单元和数据无效化处理单元。 第一个存储器具有每个字线n（n> = 2）页的存储容量。 非易失性第二存储器临时存储从主机装置写入请求的用户数据。 数据复制处理单元执行数据复制处理，包括以页为单位读出存储在第二存储器中的用户数据，并以页单元顺序地将读出的用户数据写入第一存储器。 数据无效处理单元在执行数据复制处理之后，根据每个字线的存储单元组是否存储n页的用户数据，选择需要备份的用户数据进行数据复制处理的用户数据，并且离开 所选择的用户数据在第二存储器中作为备份数据。

公开(公告)号：US08559223B2

公开(公告)日：2013-10-15

申请号：US13049504

申请日：2011-03-16

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/40

CPC分类号： G11C14/0018 ,  G11C14/00 ,  G11C16/04 ,  G11C16/0408 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529

摘要： According to one embodiment, there is provided a fusion memory including a first memory cell array formed of a NAND cell unit and a second memory cell array formed of a DRAM cell on a semiconductor substrate. The NAND cell unit is formed of a non-volatile memory cell having a two-layer gate structure in which a first gate and a second gate are stacked, and a selective transistor connecting the first and second gates of the non-volatile memory cell. The DRAM cell is formed of a cell transistor having a structure same as the structure of the selective transistor, and a MOS capacitor having a structure same as the structure of the non-volatile memory cell or the selective transistor.

摘要翻译： 根据一个实施例，提供了一种融合存储器，包括由NAND单元单元形成的第一存储单元阵列和由半导体衬底上的DRAM单元形成的第二存储单元阵列。 NAND单元单元由具有堆叠第一栅极和第二栅极的双层栅极结构的非易失性存储单元和连接非易失性存储单元的第一和第二栅极的选择晶体管构成。 DRAM单元由具有与选择晶体管的结构相同的单元晶体管和具有与非易失性存储单元或选择晶体管的结构相同的结构的MOS电容器形成。

公开(公告)号：US08255762B2

公开(公告)日：2012-08-28

申请号：US13297327

申请日：2011-11-16

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

IPC分类号： H03M13/00

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C11/005 ,  G11C16/3431

摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

摘要翻译： 本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取的数据被写回同一个存储器组时，当错误位计数超过第一阈值时 或者当数据读取计数超过第二阈值时。

公开(公告)号：US08156393B2

公开(公告)日：2012-04-10

申请号：US12513860

申请日：2007-11-28

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

IPC分类号： G11C29/00

CPC分类号： G11C16/349 ,  G06F11/008 ,  G06F11/1068

摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

摘要翻译： 提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。 存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量 擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数， 诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。