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公开(公告)号：US20100032185A1
公开(公告)日：2010-02-11
申请号：US12084292
申请日：2006-11-01
CPC分类号： H01R4/70 , H01B7/285 , H01R13/5216
摘要： The present invention is intended to enable a efficient water-sealing treatment for an on-vehicle electric cable 10, i.e., an electric cable to be mounted on a vehicle, the cable having a conductor and a sheath disposed on the outside of the conductor, regardless of a length of the electric cable. The present invention provides a method comprising the step of establishing a state where a water-sealing agent 18 with fluidity covers a gap between the conductor and the sheath in an end of the on-vehicle electric cable 10, for example, through an operation of dropping the water-sealing agent 18 onto the end of the on-vehicle electric cable 10, and the step of pressurizing an ambient air around the water-sealing agent 18 to cause the water-sealing agent 18 to penetrate into the inside of the sheath of the on-vehicle electric cable 10.
摘要翻译： 本发明旨在能够对车载电缆10（即，要安装在车辆上的电缆）进行有效的水封处理，该电缆具有布置在导体外侧的导体和护套， 不管电缆的长度如何。 本发明提供一种方法，其包括如下步骤：在车载电缆10的端部形成具有流动性的水密封剂18覆盖导体和护套之间的间隙的状态，例如通过操作 将水密封剂18滴落到车载电缆10的端部上，对密封剂18周围的周围空气进行加压，使水密封剂18渗透到护套内部 的车载电缆10。
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公开(公告)号：US09026734B2
公开(公告)日：2015-05-05
申请号：US13312129
申请日：2011-12-06
申请人： Daisuke Hashimoto
发明人： Daisuke Hashimoto
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0652 , G06F3/0679 , G06F12/08 , G06F2212/7205
摘要： According to one embodiment, a memory system includes: a memory area; a transfer processing unit that stores write data received from a host apparatus in the memory area; a delete notification buffer that accumulates a delete notification; and a delete notification processing unit. The delete notification processing unit collectively reads out a plurality of delete notifications from the delete notification buffer and classifies the read-out delete notifications for each unit area. The delete notification processing unit sequentially executes, for each unit area, processing for collectively invalidating write data related to one or more delete notifications classified in a same unit area and, in executing processing for one unit area in the processing sequentially executed for the each unit area, invalidates all write data stored in the one unit area after copying write data excluding write data to be invalidated stored in the one unit area to another unit area.
摘要翻译： 根据一个实施例，存储器系统包括：存储区域; 传送处理单元，其将从主机装置接收的写入数据存储在存储区域中; 删除通知缓冲器，累积删除通知; 和删除通知处理单元。 删除通知处理单元从删除通知缓冲器中共同读出多个删除通知，并对每个单位区域的读出删除通知进行分类。 删除通知处理单元对于每个单位区域顺序地执行用于共同使与分类在同一单位区域中的一个或多个删除通知相关的写入数据无效的处理，并且在对于每个单元顺序执行的处理中对一个单位区域执行处理 区域，在将除了存储在一个单位区域中的无效的写入数据的写入数据复制到另一单位区域之后，使存储在一个单位区域中的所有写入数据无效。
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3.发明授权Semiconductor storage device, nonvolatile semiconductor memory test method, and medium 有权半导体存储器件，非易失性半导体存储器测试方法和介质公开(公告)号：US08539315B2
公开(公告)日：2013-09-17
申请号：US13602763
申请日：2012-09-04
申请人： Daisuke Hashimoto
发明人： Daisuke Hashimoto
CPC分类号： G11C29/04 , G11C11/5628 , G11C16/00 , G11C29/06 , G11C29/08 , G11C29/44 , G11C29/52 , G11C29/82 , G11C2029/0409 , G11C2029/4402
摘要： According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block.
摘要翻译： 根据一个实施例，半导体存储装置包括非易失性半导体存储器和控制器。 非易失性半导体存储器包括能够存储用于执行正常模式或自动运行测试模式的固件的固件区域和能够存储用户数据的用户区域。 控制器从非易失性半导体存储器读取固件，并确定固件是否设置在正常模式或自动运行测试模式。 控制器使用高于正常模式下使用的电压的单元施加电压，在用户区域的每个块中重复擦除，写入和读取，并将错误发生的块输入为坏块。
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公开(公告)号：US08238137B2
公开(公告)日：2012-08-07
申请号：US12562051
申请日：2009-09-17
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on.
摘要翻译： 铁电随机存取存储器件具有第一位线，第一铁电电容器，第二位线，第二铁电电容器和第一至第四MOS晶体管。 根据存储在第一铁电电容器中的第一数据将第一位线改变为第一数据电位，根据通过反转第一数据的逻辑获得的第二数据将第二位线改变为第二数据电位，然后 第二MOS晶体管和第四MOS晶体管导通。
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公开(公告)号：US08199554B2
公开(公告)日：2012-06-12
申请号：US12876984
申请日：2010-09-07
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout.
摘要翻译： 铁电随机存取存储装置具有其中布置有由铁电电容器和晶体管形成的多个存储单元的存储单元阵列，设置字线以选择存储单元，设置板线以应用 存储单元中的铁电电容器的第一端的电压和位线被设置为从存储单元中的铁电电容器的第二端读取单元数据。 铁电随机存取存储装置具有感测放大器，其感测并放大从铁电电容器读取到位线上的信号。 铁电随机存取存储装置具有位线电位控制电路，该位线电位控制电路在该读出放大器的操作之前进行控制以在与读取信号的所选位线相邻的相邻位线上下拉电压 数据读出。
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公开(公告)号：US08059445B2
公开(公告)日：2011-11-15
申请号：US12563950
申请日：2009-09-21
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/406
摘要： A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.
摘要翻译： 根据本发明的实施例的铁电存储器包括：存储单元阵列，包括多个存储单元，并且具有多个字线，多个位线和多个板线，每个板线对应于该字中的至少两个 线路，被配置为对从所述存储器单元中选择的所选择的单元执行访问操作的访问控制电路;以及刷新控制电路，被配置为在所述访问操作的后台中执行刷新操作，所述更新单元是 从所述存储单元中选择所述刷新控制电路，所述刷新控制电路在连接到所选择的单元的板线和连接到所选择的单元的位线之间执行刷新操作，在所述访问操作之后处于相同的电位。
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公开(公告)号：US20110223056A1
公开(公告)日：2011-09-15
申请号：US12672092
申请日：2008-07-24
申请人： Yasuhiro Aruga , Daisuke Hashimoto , Koya Nomura
发明人： Yasuhiro Aruga , Daisuke Hashimoto , Koya Nomura
摘要： The present invention relates to a Cu—Ni—Sn—P-based copper alloy sheet having a specific composition, where (1) the copper alloy sheet is set to have an electrical conductivity of 32% IACS or more, a stress relaxation ratio in the direction parallel to the rolling direction of 15% or less, a 0.2%-proof stress of 500 MPa or more and an elongation of 10% or more; (2) the X-ray diffraction intensity ratio I(200)/I(220) in the sheet surface is set to be a given value or less and at the same time, anisotropy in the stress relaxation resistance characteristic is reduced by fining the grain size; (3) the texture of the copper alloy sheet is set to a texture such that the distribution density of B orientation and the sum of distribution densities of B orientation, S orientation and Cu orientation each is set to fall in a specific range and bendability is thereby enhanced; or (4) the dislocation density measured using the value obtained by dividing the half-value breadth of the X-ray diffraction intensity peak from {200} plane in the copper alloy sheet surface by the peak height is set to a given value or more and press punchability is thereby enhanced. The Cu—Ni—Sn—P-based copper alloy sheet of the present invention is excellent in the properties required for a terminal or connector and further (1) has excellent strength-ductility balance, (2) satisfies the stress relaxation resistance characteristic in the direction orthogonal to the rolling direction, (3) has excellent bendability, or (4) has excellent press punchability.
摘要翻译： 本发明涉及具有特定组成的Cu-Ni-Sn-P系铜合金板，其中（1）铜合金板的导电率设定为32％IACS以上，应力松弛率 平行于轧制方向的方向为15％以下，0.2％以上的应力为500MPa以上，伸长率为10％以上。 （2）将片材表面的X射线衍射强度比I（200）/ I（220）设定为规定值以下，同时，耐应力松弛特性的各向异性通过使 晶粒大小; （3）将铜合金板的织构设定为使得B取向的分布密度和B取向，S取向和Cu取向的分布密度之和各自落在特定范围内，弯曲性为 从而增强; 或（4）使用通过将铜合金板表面中的{200}面的X射线衍射强度峰值的半值宽度除以峰高而得到的值而测定的位错密度设定为规定值以上 从而增强了冲压性。 本发明的Cu-Ni-Sn-P系铜合金板的端子或连接器的特性优异，（1）具有优异的强度 - 延展性平衡，（2）满足 与轧制方向正交的方向，（3）具有优异的弯曲性，或者（4）具有优异的冲压冲压性。
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公开(公告)号：US20100136244A1
公开(公告)日：2010-06-03
申请号：US12627624
申请日：2009-11-30
摘要： Disclosed is an electroless nickel plating bath not containing harmful metal species. In the electroless nickel plating bath, there are contained at least an iron ion source and an iodide ion source. With the use of the electroless nickel plating bath containing at least the iron ion source and the iodide ion source, it is possible to suppress decomposition of the plating bath without using harmful metal species to stabilize the plating bath.
摘要翻译： 公开了一种不含有害金属物质的化学镀镍浴。 在化学镀镍浴中，至少含有铁离子源和碘离子源。 通过使用至少含有铁离子源和碘离子源的无电镀镍浴，可以抑制电镀液的分解，而不会使用有害的金属物质来稳定电镀液。
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公开(公告)号：US07183499B2
公开(公告)日：2007-02-27
申请号：US10557145
申请日：2004-06-15
IPC分类号： H05K9/00
CPC分类号： H05K9/0096
摘要： An electromagnetic wave shielding sheet includes a transparent substrate 11 and a metal layer 15 provided on one surface of the transparent substrate 11 through an adhesive layer 13. The metal layer 15 includes a mesh part 103 and a frame part 101 surrounding the mesh part 103. The frame part 101 includes at least one transparent part 105 that is a metal-layer-free area. Preferably, the transparent part 105 includes a metallic portion 105a in a geometric pattern. Light transmitted by or reflected from the transparent part 105 is detected, thereby the transparent part 105 can be used as a register mark for detecting the position of the mesh part 103.
摘要翻译： 电磁波屏蔽片包括透明基板11和通过粘合层13设置在透明基板11的一个表面上的金属层15.金属层15包括网状部分103和围绕网状部分103的框架部分101。 框架部101包括至少一个作为无金属层的透明部105。 优选地，透明部分105包括几何图案的金属部分105a。 检测由透明部件105透射或反射的光，透明部件105可以用作检测网状部件103的位置的对准标记。
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公开(公告)号：US09026764B2
公开(公告)日：2015-05-05
申请号：US13420808
申请日：2012-03-15
申请人： Daisuke Hashimoto
发明人： Daisuke Hashimoto
CPC分类号： G06F12/0246 , G06F12/023 , G06F12/10 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
摘要： A memory system of a embodiments includes a first storing area having physical blocks and a second storing area recording a logical to physical translation table and an erasure count table keeping data erasure count in physical blocks. The memory system of the embodiments includes a controller which, when a logical address for deletion is notified, obtains data erasure count of a deletion physical block including a deletion area specified by the physical address corresponding to the logical address, and when a physical block having a small erasure count not more than a predetermined rate of the data erasure count exists in the erasure count table, reads out valid data for the memory system in the physical block having a small erasure count onto the second storing area, writes the above data into the deletion area, and invalidates the valid data in the physical block having a small erasure count.
摘要翻译： 实施例的存储器系统包括具有物理块的第一存储区域和记录逻辑到物理转换表的第二存储区域和在物理块中保持数据擦除计数的擦除计数表。 实施例的存储器系统包括控制器，当通知用于删除的逻辑地址时，获得包括由对应于逻辑地址的物理地址指定的删除区域的删除物理块的数据擦除计数，以及当具有 在擦除计数表中存在不大于数据擦除计数的预定速率的小擦除次数，将具有小擦除次数的物理块中的存储器系统的有效数据读出到第二存储区域，将上述数据写入 删除区域，使具有小擦除次数的物理块中的有效数据无效。
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