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    Yttrium substituted barium thioaluminate phosphor materials
    7.
    发明授权
    Yttrium substituted barium thioaluminate phosphor materials 失效
    钇取代硫代铝酸钠磷光体材料

    公开(公告)号：US06982124B2

    公开(公告)日：2006-01-03

    申请号：US10397148

    申请日：2003-03-26

    申请人： M. Nakua Abdul ,  Dan Daeweon Cheong

    发明人： M. Nakua Abdul ,  Dan Daeweon Cheong

    IPC分类号： H05B33/12

    CPC分类号： H05B33/14 ,  C09K11/752 ,  C09K11/7768 ,  C09K11/7786 ,  C09K11/892 ,  H05B33/22 ,  H05B33/26 ,  Y10S428/917

    摘要： A thin film phosphor for an electroluminescent device, the phosphor being selected from the group consisting of thiasluminates, thiogallates and thioindates having at least one cation selected from elements of Groups IIA and IIB of the Periodic Table of Elements. The phosphor being activated by a rare earth metal and containing a Group IIIB element as a partial substitute for a portion of aluminum, gallium or indium of the thiogallate, thioindate and thioaluminate. The phosphor provides improved luminance. An electroluminescent device consisting of the thin film phosphor on a substrate is also described.

    摘要翻译： 一种用于电致发光器件的薄膜荧光体，所述荧光体选自具有至少一种选自元素周期表IIA和IIB族元素的至少一种阳离子的硫柳汞，硫代镓酸盐和硫茚酸盐。 荧光体被稀土金属活化并含有IIIB族元素作为硫代镓酸盐，硫酸盐和硫代铝酸盐的一部分铝，镓或铟的部分替代物。 荧光体提供改善的亮度。 还描述了由基底上的薄膜荧光体组成的电致发光器件。

    Multiple source deposition process
    8.
    发明授权
    Multiple source deposition process 有权

    公开(公告)号：US06610352B2

    公开(公告)日：2003-08-26

    申请号：US09747315

    申请日：2000-12-22

    申请人： Dan Daeweon Cheong

    发明人： Dan Daeweon Cheong

    IPC分类号： C23C1454

    CPC分类号： C09K11/7731 ,  C09K11/08 ,  C09K11/7734 ,  C23C14/0623 ,  C23C14/30 ,  C23C14/548 ,  H01B3/02

    摘要： A method for the deposition of a thin film of a pre-determined composition e.g. a phosphor, onto a substrate, in which the composition is a ternary, quaternary or higher composition, especially a composition selected from the group consisting of thioaluminates, thiogallates and thioindates of at least one element from Groups IIA and IIB of the Periodic Table. In the embodiment, the method comprises placing a pellet of at least one sulfide on a first source and placing a pellet of at least one sulfide on a second source, with one pellet containing dopant. Vapor deposition onto the substrate is effected with separate electron beams. The rate of vaporizing of the sulfides is monitored with separate shielded coating rate monitors. The temperature of the sources is controlled to obtain the composition on the substrate. The method is particularly used for deposition of ternary or quaternary phosphors on substantially opaque substrates in electroluminescent devices.

    BASE STRUCTURE FOR III-V SEMICONDUCTOR DEVICES ON GROUP IV SUBSTRATES AND METHOD OF FABRICATION THEREOF
    9.
    发明申请
    BASE STRUCTURE FOR III-V SEMICONDUCTOR DEVICES ON GROUP IV SUBSTRATES AND METHOD OF FABRICATION THEREOF 审中-公开
    第IV组基板上的III-V半导体器件的基本结构及其制造方法

    公开(公告)号：US20100263707A1

    公开(公告)日：2010-10-21

    申请号：US12762256

    申请日：2010-04-16

    申请人： Dan Daeweon Cheong ,  Rafael Nathan Kleiman ,  Manuela Peter ,  Nicholas Komarnycky ,  Bradley Joseph Robinson ,  John Stewart Preston

    发明人： Dan Daeweon Cheong ,  Rafael Nathan Kleiman ,  Manuela Peter ,  Nicholas Komarnycky ,  Bradley Joseph Robinson ,  John Stewart Preston

    IPC分类号： H01L31/05 ,  C30B23/02 ,  H01L21/20

    CPC分类号： C30B25/183 ,  C30B23/02 ,  C30B23/025 ,  C30B29/40 ,  C30B29/42 ,  C30B29/44 ,  H01L31/1852 ,  Y02E10/544

    摘要： The structure presented herein provides a base structure for semiconductor devices, in particular for III-V semiconductor devices or for a combination of III-V and Group IV semiconductor devices. The fabrication method for a base substrate comprises a buffer layer, a nucleation layer, a Group IV substrate and possibly a dopant layer. There are, in a general aspect, two growth steps: firstly the growth of a lattice-matched III-V material on a Group IV substrate, followed by secondly the growth of a lattice-mismatched III-V layer. The first layer, called the nucleation layer, is lattice-matched or closely lattice-matched to the Group IV substrate while the following layer, the buffer layer, deposited on top of the nucleation layer, is lattice-mismatched to the nucleation layer. The nucleation layer can further be used as a dopant source to the Group IV substrate, creating a p-n junction in the substrate through diffusion. Alternatively a separate dopant layer may be introduced.

    摘要翻译： 本文中给出的结构提供了半导体器件的基础结构，特别是对于III-V半导体器件或III-V和IV族半导体器件的组合。 基底衬底的制造方法包括缓冲层，成核层，第IV族衬底和可能的掺杂剂层。 在一般方面，存在两个生长步骤：首先在IV族衬底上生长晶格匹配的III-V材料，其次是晶格失配的III-V层的生长。 称为成核层的第一层与第IV族基质晶格匹配或紧密地晶格匹配，而沉积在成核层顶部的下一层缓冲层与成核层晶格失配。 成核层可以进一步用作第IV族衬底的掺杂剂源，通过扩散在衬底中产生p-n结。 或者，可以引入单独的掺杂剂层。