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公开(公告)号：US07321512B2
公开(公告)日：2008-01-22
申请号：US11381426
申请日：2006-05-03
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C8/14 , G11C11/5642 , G11C16/08 , G11C16/30
摘要： A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp. A respective local ramp generating circuit is provided for each array sector and for the array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.
摘要翻译： 非易失性存储器件包括被组织成多个阵列扇区的存储器单元的阵列，每个阵列扇区通过阵列字线被单独寻址。 参考单元阵列可通过参考字线寻址。 为每个阵列扇区提供相应的电压斜坡发生器，用于在阵列字线上产生用于读取其中的存储单元的电压斜坡，并且为每个参考单元阵列提供参考单元阵列，用于在其上的参考单元的基准字线上产生电压斜坡 。 相应的行解码电路耦合在每个相应的电压斜坡发生器和对应的参考字线或阵列字线之间。 电流发生器产生要注入到选定的阵列扇区中的电路节点上的参考电池阵列的电路节点上的电流，以在电路节点上产生类似于所产生的电压斜坡的电压斜坡。 为每个阵列扇区和参考单元阵列提供相应的本地斜坡发生电路，并且将基于对应的寻址阵列字线或参考字线的电路节点的电荷的充电电流传送到相应的行解码器 字线
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公开(公告)号：US20060250852A1
公开(公告)日：2006-11-09
申请号：US11381426
申请日：2006-05-03
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C8/14 , G11C11/5642 , G11C16/08 , G11C16/30
摘要： A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective volage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp. A respective local ramp generating circuit is prtovided for each array sector and for the array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.
摘要翻译： 非易失性存储器件包括被组织成多个阵列扇区的存储器单元的阵列，每个阵列扇区通过阵列字线被单独寻址。 参考单元阵列可通过参考字线寻址。 为每个阵列扇区提供相应的电压斜坡发生器，用于在阵列字线上产生用于读取其中的存储单元的电压斜坡，并且为每个参考单元阵列提供参考单元阵列，用于在其上的参考单元的基准字线上产生电压斜坡 。 相应的行解码电路耦合在每个相应的电压斜坡发生器和相应的参考字线或阵列字线之间。 电流发生器产生要注入到选定的阵列扇区中的电路节点上的参考电池阵列的电路节点上的电流，以在电路节点上产生类似于所产生的电压斜坡的电压斜坡。 为每个阵列扇区和参考单元阵列提供相应的本地斜坡发生电路，并且将基于相应寻址的阵列字线或参考字线的电路节点的电容的充电电流分配给相应的行解码器 字线
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公开(公告)号：US20050030809A1
公开(公告)日：2005-02-10
申请号：US10913128
申请日：2004-08-06
摘要： A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop, for controlling the memory bit line potential during the precharge phase. A same circuit element is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.
摘要翻译： 一种用于半导体存储器的感测电路，包括一个电路分支，用于电耦合到已连接到要感测的存储器单元的存储器位线。 提供位线预充电电路，用于在存储器单元感测操作的预充电阶段将存储器位线预充电到预定电位。 评估电路与用于评估存储器单元感测操作的评估阶段期间在存储器位线上产生的电量的存储器位线相关联; 在存储位线上产生的电量表示存储单元的信息内容。 位线预充电电路适于对存储器位线进行充电和放电，使得在预充电阶段开始时的存储位线初始电位无论达到预定的位线电位。 位线预充电电路适于根据存储器位线电位和预定位线电位之间的差异来对存储器位线进行充电和放电。 至少预充电电路包括预充电负反馈控制回路，用于在预充电阶段期间控制存储器位线电位。 提供了相同的电路元件，其在预充电阶段期间控制存储器位线电位，并且在存储器单元感测操作的评估阶段期间评估电量。
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公开(公告)号：US07272059B2
公开(公告)日：2007-09-18
申请号：US10913128
申请日：2004-08-06
IPC分类号： G11C7/00
摘要： A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop, for controlling the memory bit line potential during the precharge phase. A same circuit element is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.
摘要翻译： 一种用于半导体存储器的感测电路，包括一个电路分支，用于电耦合到已连接到要感测的存储器单元的存储器位线。 提供位线预充电电路，用于在存储器单元感测操作的预充电阶段将存储器位线预充电到预定电位。 评估电路与用于评估存储器单元感测操作的评估阶段期间在存储器位线上产生的电量的存储器位线相关联; 在存储位线上产生的电量表示存储单元的信息内容。 位线预充电电路适于对存储器位线进行充电和放电，使得在预充电阶段开始时的存储位线初始电位无论达到预定的位线电位。 位线预充电电路适于根据存储器位线电位和预定位线电位之间的差异来对存储器位线进行充电和放电。 至少预充电电路包括预充电负反馈控制回路，用于在预充电阶段期间控制存储器位线电位。 提供了相同的电路元件，其在预充电阶段期间控制存储器位线电位，并且在存储器单元感测操作的评估阶段期间评估电量。
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公开(公告)号：US6014044A
公开(公告)日：2000-01-11
申请号：US960186
申请日：1997-10-29
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Philip Leong , Marco Onorato , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Philip Leong , Marco Onorato , Pier Luigi Rolandi , Marco Sabatini
CPC分类号： H03K5/08 , H03K19/0027 , H03M1/36 , H03M1/46
摘要： This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.
摘要翻译： 本发明涉及具有用于模拟信号和数字信号的输出的电压比较器，包括一个反相器，该反相器具有耦合到比较器输入的输入端和耦合到该比较器输出的输出，并且包括至少两个MOS晶体管 彼此耦合，两个MOS晶体管中的至少一个是浮栅型。
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6.发明授权Method for programming a memory device suitable to minimize floating gate coupling and memory device 有权用于编程适于最小化浮动栅极耦合和存储器件的存储器件的方法公开(公告)号：US07688633B2
公开(公告)日：2010-03-30
申请号：US11732486
申请日：2007-04-02
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621
摘要： Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.
摘要翻译： 一种用于编程存储器件的方法的实施例，该存储器件包括在彼此电容性分离的单元的缓冲器中分开的存储器单元的矩阵，该方法包括：首先对属于缓冲器的所述单元进行编程; 属于所述缓冲器的所述单元的第二编程; 所述第一编程的步骤是以具有第一音调的斜坡栅极电压发生的，并且对具有较高阈值分布的所述缓冲器的所述单元进行编程，并且所述第二编程步骤以斜距低于间距的斜坡栅极电压发生。
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7.发明申请Method for programming a memory device suitable to minimize floating gate coupling and memory device 有权用于编程适于最小化浮动栅极耦合和存储器件的存储器件的方法公开(公告)号：US20070247917A1
公开(公告)日：2007-10-25
申请号：US11732486
申请日：2007-04-02
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621
摘要： Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.
摘要翻译： 一种用于编程存储器件的方法的实施例，该存储器件包括在彼此电容性分离的单元的缓冲器中分开的存储器单元的矩阵，该方法包括：首先对属于缓冲器的所述单元进行编程; 属于所述缓冲器的所述单元的第二编程; 所述第一编程的步骤是以具有第一音调的斜坡栅极电压发生的，并且对具有较高阈值分布的所述缓冲器的所述单元进行编程，并且所述第二编程步骤以斜距低于间距的斜坡栅极电压发生。
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