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公开(公告)号：US5297269A
公开(公告)日：1994-03-22
申请号：US66597
申请日：1993-05-24
申请人： Darrel D. Donaldson , Mark N. Howard , David A. Orbits , John M. Parchem , David M. Robinson , Douglas Williams
发明人： Darrel D. Donaldson , Mark N. Howard , David A. Orbits , John M. Parchem , David M. Robinson , Douglas Williams
CPC分类号： G06F12/0828
摘要： A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.
摘要翻译： 用于多处理器系统的缓存一致性协议，其提供读/写，只读和过渡数据状态，以及用于将这些状态的指示存储在主存储器中的存储器目录中。 当处理器从主存储器请求另一个处理器的缓存中的数据块并且请求正在等待完成时，发生过渡数据状态。 在第一个请求的未决期间，数据块的所有后续读取请求被禁止，直到完成第一个请求。 在每个数据块的存储器目录中还提供了用于识别拥有所讨论的数据块的处理器的字段。 数据块所有权信息用于确定所请求的数据所在的位置。
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公开(公告)号：US5229926A
公开(公告)日：1993-07-20
申请号：US862004
申请日：1992-04-01
IPC分类号： H01L27/02 , H03K19/003
CPC分类号： H01L27/0218 , H03K19/00315 , H03K19/00361
摘要： A power supply interlock technique for an electronic system which uses metal oxide semiconductor (MOS) logic circuits require two or more different supply voltages, and where each circuit board module contains its own power supplies. An open-collector enable signal is both controlled and sensed by each of the modules. The enable signal is set true when all of the supplies in the system are operating properly. However, the enable signal is set false by any one of the modules if one of the higher voltage supplies on that module is malfunctioning. The enable line also controls the lower voltage power supplies in each module. None of the lower voltage power supplies is thus permitted to operate until the enable line is set true, which occurs only when all of the modules indicate they have an operating high voltage supply available. As a result, latch-up of parasitic transistors in the circuits which drive logic signals on a system bus is avoided.
摘要翻译： 用于使用金属氧化物半导体（MOS）逻辑电路的电子系统的电源互锁技术需要两个或多个不同的电源电压，并且其中每个电路板模块包含其自己的电源。 开放集电极使能信号由每个模块进行控制和感测。 当系统中的所有电源正常工作时，使能信号设置为真。 但是，如果该模块上的较高电压源之一发生故障，则使能信号由任何一个模块置为false。 使能线还可以控制每个模块中的较低电压电源。 因此，只有当所有模块都表明它们具有可用的工作高压电源时，才允许低电压电源才能运行，直到使能线设置为真。 结果，避免了在系统总线上驱动逻辑信号的电路中的寄生晶体管的锁存。
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公开(公告)号：US4922449A
公开(公告)日：1990-05-01
申请号：US368956
申请日：1989-06-13
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , G06F13/4077
摘要： A system for communicating between a plurality of nodes in a computer, each node including logic circuitry for transmitting and receiving data. The subject system includes (1) a backplane bus for carrying the data between the nodes, (2) a driver in each node and a current source circuit coupled to the bus which drive the bus in parallel to decrease the transition time of the data transmitted onto the bus, and (3) coupling resistors individually coupling the bus to the driver in each node and providing impedance matching between the bus and nodes and permitting driver overlap at the bus so that the higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized and resistors are used to terminate the ends of the bus to the supply voltages.
摘要翻译： 一种用于在计算机中的多个节点之间通信的系统，每个节点包括用于发送和接收数据的逻辑电路。 主题系统包括（1）用于在节点之间传送数据的背板总线，（2）每个节点中的驱动器和耦合到总线的电流源电路，其并行驱动总线以减少传输的数据的转换时间 到总线上，（3）耦合电阻将各总线连接到每个节点中的驱动器，并提供总线与节点之间的阻抗匹配，并允许总线上的驱动器重叠，从而发生更高的速度和更低的功耗。 在优选实施例中，使用CMOS逻辑电路，并且使用电阻器将总线的端部端接到电源电压。
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4.发明授权Node with coupling resistor for limiting current flow through driver during overlap condition 失效具有耦合电阻的节点，用于在重叠条件期间限制通过驱动器的电流
公开(公告)号：US5146563A
公开(公告)日：1992-09-08
申请号：US327425
申请日：1989-03-23
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , G06F13/4077 , Y02B60/1228 , Y02B60/1235
摘要： A node includes logic circitry for transmitting and receiving data on a backplane bus. The driver in the transmitting logic in the node acts with the current source provided by the bus to decrease the transition time of the data transmitted onto the bus. A coupling resistor is included in the node for individually coupling the driver in the node to the bus for limiting voltage excursions on the bus and providing impedance matching between the node and bus and permitting driver overlap at the bus so that higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized.
摘要翻译： 节点包括用于在背板总线上发送和接收数据的逻辑循环。 节点中的发送逻辑中的驱动器与由总线提供的当前源起作用，以减少发送到总线上的数据的转换时间。 节点中包括耦合电阻，用于将节点中的驱动器单独耦合到总线，以限制总线上的电压偏移，并提供节点和总线之间的阻抗匹配，并允许驱动器在总线上重叠，从而实现更高的速度和更低的功耗 发生。 在优选实施例中，利用CMOS逻辑电路。
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公开(公告)号：US4837736A
公开(公告)日：1989-06-06
申请号：US44953
申请日：1987-05-01
CPC分类号： G06F13/4072 , G06F13/36
摘要： A system for communicating between a plurality of nodes in a computer, each node including logic circuitry or transmitting and receiving data at first and second logic levels. The system includes an arbiter coupled to the nodes for detecting a lack of request activity from the nodes. A default generator is connected to the arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.
摘要翻译： 一种用于在计算机中的多个节点之间通信的系统，每个节点包括逻辑电路或者在第一和第二逻辑电平处发送和接收数据。 该系统包括耦合到节点的仲裁器，用于检测节点中缺少请求活动。 默认生成器连接到仲裁器，并响应于缺少请求活动，并且在总线上不执行多周期数据传输，并使总线被驱动到第一和第二逻辑电平之一。
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公开(公告)号：US4774422A
公开(公告)日：1988-09-27
申请号：US44780
申请日：1987-05-01
IPC分类号： G06F3/00 , G06F13/40 , H03K17/16 , H03K19/017 , H03K19/092
CPC分类号： G06F13/4072
摘要： Bus interface apparatus is provided to drive a high speed bus with two nonoverlapping clock signals. The apparatus takes advantage of the inherent bus capacitance which will temporarily hold data signals placed on the bus by using bus interface circuitry having high input and output impedances. That circuitry can thus be activated by coincident signals.
摘要翻译： 提供总线接口装置以驱动具有两个不重叠时钟信号的高速总线。 该装置利用通过使用具有高输入和输出阻抗的总线接口电路临时保持放置在总线上的数据信号的固有总线电容。 因此，可以通过重合的信号激活该电路。
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公开(公告)号：US5003467A
公开(公告)日：1991-03-26
申请号：US44468
申请日：1987-05-01
IPC分类号： G06F13/40
CPC分类号： G06F13/4063
摘要： A node for communicating with a plurality of other nodes in a computer, the node including logic circuitry for transmitting and receiving data at first and second logic levels. A default generator is connected to an arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.
摘要翻译： 一种用于与计算机中的多个其他节点通信的节点，所述节点包括用于在第一和第二逻辑电平处发送和接收数据的逻辑电路。 默认发生器连接到仲裁器，并响应于缺少请求活动，并且在总线上不执行多周期数据传输，并使总线被驱动到第一和第二逻辑电平之一。
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8.发明授权Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers 失效前瞻性总线仲裁系统，通过多周期数据传输的总线周期扩展覆盖条件访问授权
公开(公告)号：US4947368A
公开(公告)日：1990-08-07
申请号：US44490
申请日：1987-05-01
IPC分类号： G06F15/16 , G06F9/52 , G06F13/26 , G06F13/362 , G06F13/364 , G06F13/366 , G06F15/177
CPC分类号： G06F13/364
摘要： A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.
摘要翻译： 用于获取访问总线的节点。 在该仲裁方法中，节点接收条件授权。 节点确定对总线的访问是否实际传输到它。 节点包含分布式逻辑，检查扩展总线周期信号，以确定它是否可以成为在总线上传输消息的发送器。 当节点成为发射机时，即使执行多周期传输，即使其他可能具有较高优先级的节点需要访问总线，它也会生成一个扩展总线周期信号，以保持对总线的访问。
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公开(公告)号：US4829515A
公开(公告)日：1989-05-09
申请号：US44467
申请日：1987-05-01
CPC分类号： G06F13/4027
摘要： An interface system between a high speed user bus and a system bus is provided to present to the user bus a picture of the data transferred on the system bus every clock cycle of that system bus. The interface system also allows the user bus to transfer data back to the system bus during selected bus cycles. By using a single pin connection to the system bus, the user bus can send communications back to itself by way of the system bus.
摘要翻译： 提供高速用户总线和系统总线之间的接口系统，以便在系统总线的每个时钟周期向用户总线呈现在系统总线上传送的数据的图像。 接口系统还允许用户总线在选择的总线周期期间将数据传送回系统总线。 通过使用与系统总线的单引脚连接，用户总线可以通过系统总线将通信发送回自身。
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10.发明授权Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfer 失效前瞻性总线仲裁系统，通过总线周期扩展覆盖多周期数据传输的条件访问授权
公开(公告)号：US5111424A
公开(公告)日：1992-05-05
申请号：US483813
申请日：1990-02-23
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorites, require access to the bus.
摘要翻译： 用于获取访问总线的节点。 在该仲裁方法中，节点接收条件授权。 节点确定对总线的访问是否实际传输到它。 节点包含分布式逻辑，检查扩展总线周期信号，以确定它是否可以成为在总线上传输消息的发送器。 当节点成为发射机时，即使执行多周期传输，即使其他节点（也许具有较高的优先级）也需要访问总线，它会生成一个扩展总线周期信号，以保持对总线的访问。
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