公开(公告)号：US20050013187A1

公开(公告)日：2005-01-20

申请号：US10604414

申请日：2003-07-18

申请人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

发明人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G11C17/00 ,  G11C17/16 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method and electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch and other logic components the eFuse circuit. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output generated by the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain depending on whether the next fuse is to be blown. Accordingly, rather than serially shifting through each fuse latch within the device, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

摘要翻译： 一种用于减少使用冗余eFuse电路制造的半导体器件的测试时间的方法和电熔丝电路设计。 除了保险丝锁存器和图案锁存器以及eFuse电路的其他逻辑元件之外，在每个eFuse电路上还提供两对一多路复用器（MUX）。 保险丝图案锁存器中存储有要熔断保险丝的信息。 由模式锁存器产生的输出与程序输入进行“与”运算以提供MUX的选择信号。 基于选择信号，MUX允许移位的“1”转到下一个锁存器，或者旁路下一个锁存器或锁存在换档链中，这取决于下一个保险丝是否被熔断。 因此，本发明不仅可以串联地转换器件内的每个熔丝锁存器，而且仅使与熔断器相关联的熔丝锁存器能够保持传输“1”到下一个eFuse电路的传输。

公开(公告)号：US20050030065A1

公开(公告)日：2005-02-10

申请号：US10604621

申请日：2003-08-05

申请人： Darren Anand ,  John Barth

发明人： Darren Anand ,  John Barth

IPC分类号： H03K19/00 ,  H03K19/096

CPC分类号： H03K19/0008

摘要： A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transmitted from said transmitting storage elements. Encoding logic is used for encoding the transmitted data from the transmitting storage elements, wherein the encoded transmitted data is coupled to a plurality of data lines. The encoding logic is further configured so as to result in only one of the plurality of data lines being activated during a given data transmission cycle.

摘要翻译： 自定时数据传输系统包括由相应的多个发送存储元件发送的至少两个数据位定义的数据位组。 相应的多个数据接收存储元件接收从所述发送存储元件发送的数据。 编码逻辑用于对来自发送存储元件的发送数据进行编码，其中编码的发送数据耦合到多条数据线。 编码逻辑被进一步配置为使得在给定的数据传输周期期间只有多条数据线中的一条被激活。

公开(公告)号：US20050050415A1

公开(公告)日：2005-03-03

申请号：US10604908

申请日：2003-08-26

申请人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

发明人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318544

摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

摘要翻译： 一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。 电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。 本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。 低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

公开(公告)号：US20060124982A1

公开(公告)日：2006-06-15

申请号：US10905094

申请日：2004-12-15

申请人： Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

发明人： Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

IPC分类号： H01L29/94 ,  H01L27/108

CPC分类号： H01L27/0805 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

摘要翻译： 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

公开(公告)号：US20050226024A1

公开(公告)日：2005-10-13

申请号：US10708917

申请日：2004-03-31

申请人： John Barth

发明人： John Barth

IPC分类号： G11C5/06 ,  G11C7/18 ,  G11C11/4097

CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C11/4097

摘要： A bitline structure for a memory array includes a first pair of complementary bitlines and a second pair of complementary bitlines. Both the first and second pair of complementary bitlines have a twist at a location corresponding to about ¼ of the total length of the bitline structure. The second pair of complementary bitlines further have a twist at a location corresponding to about ½ of the total length of the bitline structure, and both the first and second pair of complementary bitlines have a twist at a location corresponding to about ¾ the total length of the bitline structure.

摘要翻译： 用于存储器阵列的位线结构包括第一对互补位线和第二对互补位线。 第一对和第二对互补位线在对应于位线结构的总长度的约1/4的位置处具有扭曲。 第二对互补位线在对应于位线结构的总长度的大约1/2的位置处进一步具有扭曲，并且第一对互补位线对和第二对补充位线对之间的扭曲在相当于 位线结构。

公开(公告)号：US20070025170A1

公开(公告)日：2007-02-01

申请号：US11190542

申请日：2005-07-27

申请人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

发明人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

公开(公告)号：US20050207210A1

公开(公告)日：2005-09-22

申请号：US10708713

申请日：2004-03-19

申请人： John Barth ,  George Braceras ,  Harold Pilo

发明人： John Barth ,  George Braceras ,  Harold Pilo

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.

摘要翻译： 在静态随机存取存储器（SRAM）单元的读取操作期间用于小信号感测的方法包括将一对互补读出放大器数据线耦合到与SRAM单元相关联的对应的一对互补位线，并且将读出放大器设置为 放大在感测放大器数据线上产生的信号，其中位线对在读出放大器设置时保持耦合到读出放大器数据线。

公开(公告)号：US12018703B2

公开(公告)日：2024-06-25

申请号：US16925487

申请日：2020-07-10

申请人： Kevin Kusiak ,  Victor Acosta ,  John Barth ,  John Allen

发明人： Kevin Kusiak ,  Victor Acosta ,  John Barth ,  John Allen

IPC分类号： F15B1/033 ,  F15B1/02

CPC分类号： F15B1/033 ,  F15B1/024 ,  F15B2211/20515 ,  F15B2211/20546 ,  F15B2211/20576 ,  F15B2211/212 ,  F15B2211/5151

摘要： A marine hydraulic system and method of use for reducing cyclic loading of the pump(s) and motor(s) and an amount of accumulator storage required in a hydraulic system. A closed loop logic controller comprising at least one control algorithm for each pump/motor pair utilized in a single hydraulic system is utilized to reduce load fluctuations on the motors, allow the use of common pressure compensated, variable displacement (VDH) pumps, reduce the number and/or volume of system accumulators and equalize wear throughout the system.

公开(公告)号：US20220010816A1

公开(公告)日：2022-01-13

申请号：US16925487

申请日：2020-07-10

申请人： Kevin Kusiak ,  Victor Acosta ,  John Barth ,  John Allen

发明人： Kevin Kusiak ,  Victor Acosta ,  John Barth ,  John Allen

IPC分类号： F15B1/033 ,  F15B1/02

摘要： A marine hydraulic system and method of use for reducing cyclic loading of the pump(s) and motor(s) and an amount of accumulator storage required in a hydraulic system. A closed loop logic controller comprising at least one control algorithm for each pump/motor pair utilized in a single hydraulic system is utilized to reduce load fluctuations on the motors, allow the use of common pressure compensated, variable displacement (VDH) pumps, reduce the number and/or volume of system accumulators and equalize wear throughout the system.

公开(公告)号：US20070223298A1

公开(公告)日：2007-09-27

申请号：US11754422

申请日：2007-05-29

申请人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

发明人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。