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1.发明申请公开(公告)号：US20080002451A1
公开(公告)日：2008-01-03
申请号：US11427849
申请日：2006-06-30
IPC分类号： G11C17/00
摘要： A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译： 差分保险丝感测系统包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到熔丝支脚的第一输入节点和耦合到参考的第二节点的差分读出放大器 电压。 保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压 每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。
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2.发明授权公开(公告)号：US07477555B2
公开(公告)日：2009-01-13
申请号：US11427849
申请日：2006-06-30
IPC分类号： G11C7/00
摘要： A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译： 差分保险丝感测系统包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到熔丝支脚的第一输入节点和耦合到参考的第二节点的差分读出放大器 电压。 保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压 每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。
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3.发明授权公开(公告)号：US07917806B2
公开(公告)日：2011-03-29
申请号：US11958680
申请日：2007-12-18
IPC分类号： G06F11/00
CPC分类号： G01R19/16552 , G11C11/401 , G11C29/02 , G11C29/021 , G11C29/44 , G11C2029/0401 , G11C2029/4402
摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.
摘要翻译： 多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。 接收数字符合性信号，每个合规信号与多个片上电源之一相关联。 每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。 合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。 输出电源状态信号。 如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。 如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。 如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。
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公开(公告)号：US08484543B2
公开(公告)日：2013-07-09
申请号：US13204929
申请日：2011-08-08
IPC分类号： H03M13/00
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译： 选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。 可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。 每个状态机可以包括诸如“粘性位”的指示符，当其遇到类型的校正时可以被激活。 指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。
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5.发明授权公开(公告)号：US07453973B2
公开(公告)日：2008-11-18
申请号：US11533907
申请日：2006-09-21
申请人： Darren L. Anand , John R. Goss , Peter O. Jacobsen , Michael R. Ouellette , Thomas G. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jacobsen , Michael R. Ouellette , Thomas G. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。
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6.发明授权公开(公告)号：US07170299B1
公开(公告)日：2007-01-30
申请号：US11276120
申请日：2006-02-15
CPC分类号： G11C17/16 , G01R31/07 , G11C17/165 , G11C17/18 , G11C29/02 , G11C29/027 , G11C29/028 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A system, method and program product for adjusting an environmental variable of a fuse blow of an electronic fuse are disclosed. A mimic NFET is coupled to a fuse blow source voltage line, a fuse blow gate voltage line, and a chip ground in the same manner as the electronic fuse, except that the mimic NFET is not attached to a poly fuse link. The on current (ion) and off current (ioff) of the mimic NFET are measured to determine a blow current of the electronic fuse. The environmental variable is adjusted based on the determined blow current.
摘要翻译： 公开了一种用于调整电子保险丝熔断器的环境变量的系统，方法和程序产品。 模拟NFET以与电子熔断器相同的方式耦合到保险丝熔断器电压线，保险丝熔断栅极电压线和芯片接地，除了模拟NFET未连接到多晶硅熔丝链路。 测量模拟NFET的导通电流（离子）和截止电流（ioff），以确定电子熔断器的吹扫电流。 环境变量根据确定的吹扫电流进行调整。
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7.发明授权Multi-bank random access memory structure with global and local signal buffering for improved performance 有权具有全局和本地信号缓冲的多存储体随机存取存储器结构，以提高性能公开(公告)号：US08649239B2
公开(公告)日：2014-02-11
申请号：US13479448
申请日：2012-05-24
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译： 公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。 具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组 连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲 并且因此是真实的信号。 在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。
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8.发明授权Method for separating shift and scan paths on scan-only, single port LSSD latches 失效用于在仅扫描单端口LSSD锁存器上分离移位和扫描路径的方法公开(公告)号：US07243279B2
公开(公告)日：2007-07-10
申请号：US10604908
申请日：2003-08-26
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.
摘要翻译： 一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。 电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。 本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。 低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。
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9.发明授权Method of electrically blowing fuses under control of an on-chip tester interface apparatus 有权在片上测试仪接口装置的控制下电熔熔丝的方法公开(公告)号：US06768694B2
公开(公告)日：2004-07-27
申请号：US10265591
申请日：2002-10-07
申请人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
发明人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C700
CPC分类号： G11C29/027 , G11C17/18 , G11C29/56 , G11C29/785 , G11C2029/1208
摘要： A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.
摘要翻译： 公开了一种芯片修复系统，专为自动化测试设备而独立应用于许多独特的非常密集的ASIC设备，在高周转环境中。 在测试期间，系统将控制芯片内置的自检（BIST）引擎收集和压缩修复数据，程序保险丝，并最终解压缩并重新加载后保险丝测试的修复数据。 在最终使用应用程序中，该系统在上电时或在系统请求下解压缩加载修复数据。
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公开(公告)号：US20130042166A1
公开(公告)日：2013-02-14
申请号：US13204929
申请日：2011-08-08
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译： 选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。 可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。 每个状态机可以包括当遇到其类型的校正时可以被激活的指示器，例如粘性位。 指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。
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