公开(公告)号：US5386832A

公开(公告)日：1995-02-07

申请号：US75662

申请日：1993-06-11

申请人： David A. Wagner ,  Martin A. Baker ,  Peter A. Burke ,  R. Amour Forse ,  John D. Palombo ,  Bruce R. Bistrian

发明人： David A. Wagner ,  Martin A. Baker ,  Peter A. Burke ,  R. Amour Forse ,  John D. Palombo ,  Bruce R. Bistrian

IPC分类号： A61K51/04 ,  A61K51/12 ,  A61B5/08 ,  A61B6/00

CPC分类号： A61K51/1206 ,  A61K51/0406

摘要： A test for determining hepatic function has been developed. This test uses oral administration of isotope labeled phenylalanine or tyrosine, particularly .sup.13 C-phenylalanine, in a rapid breath test. In the preferred mode, the breath sample is analyzed using a mass spectrometer and compared with a standard. The breath test provides a dynamic rather than static determination of hepatic function and can be used for both early and late stage liver problems.

摘要翻译： 已经开发了一种测定肝功能的试验。 该测试在快速呼吸试验中使用同位素标记的苯丙氨酸或酪氨酸，特别是13 C-苯丙氨酸的口服给药。 在优选模式中，使用质谱仪分析呼吸样本并与标准进行比较。 呼吸试验提供肝功能的动态而非静态测定，可用于早期和晚期肝脏问题。

公开(公告)号：US08685822B2

公开(公告)日：2014-04-01

申请号：US13022628

申请日：2011-02-07

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L21/336

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

公开(公告)号：US07988920B2

公开(公告)日：2011-08-02

申请号：US12939246

申请日：2010-11-04

申请人： Michael A. Centanni ,  Peter A. Burke

发明人： Michael A. Centanni ,  Peter A. Burke

IPC分类号： A62B7/08 ,  A61L9/00

CPC分类号： A61L2/208 ,  A61L2/202 ,  A61L2/206 ,  A61L9/015 ,  A61L2202/13

摘要： A method and apparatus for aerating a region exposed to a gaseous/vaporous sterilant. A catalytic destroyer and a reactive chemical unit are used to reduce the concentration of the gaseous/vaporous sterilant within the region. The reactive chemical unit includes a chemistry that is chemically reactive with the gaseous/vaporous sterilant. In one embodiment, the gaseous/vaporous sterilant is vaporized hydrogen peroxide and the chemistry of the reactive chemical unit includes thiosulfate and iodide.

摘要翻译： 用于对暴露于气体/蒸气灭菌剂的区域进行曝气的方法和装置。 催化破坏剂和反应性化学单元用于降低该区域内气态/蒸气灭菌剂的浓度。 反应性化学单元包括与气态/蒸气灭菌剂化学反应的化学物质。 在一个实施方案中，气态/蒸气灭菌剂是蒸发的过氧化氢，并且反应性化学单元的化学性质包括硫代硫酸盐和碘化物。

公开(公告)号：US07897462B2

公开(公告)日：2011-03-01

申请号：US12271083

申请日：2008-11-14

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L21/336

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

公开(公告)号：US07728433B2

公开(公告)日：2010-06-01

申请号：US11736402

申请日：2007-04-17

申请人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

发明人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

IPC分类号： H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改善的对铜的粘合性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

公开(公告)号：US20100123192A1

公开(公告)日：2010-05-20

申请号：US12271083

申请日：2008-11-14

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

公开(公告)号：US20090315142A1

公开(公告)日：2009-12-24

申请号：US12549100

申请日：2009-08-27

申请人： Peter A. Burke ,  Sallie Hose ,  Sudhama C. Shastri

发明人： Peter A. Burke ,  Sallie Hose ,  Sudhama C. Shastri

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76846 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

摘要翻译： 一种包括集成无源器件的半导体部件和用于制造半导体部件的方法。 在衬底上方制造垂直集成的无源器件。 根据一个实施例，在基板上方的第一电平中制造电阻器，在垂直于第一电平的第二电平上制造电容器，并且在垂直于第二电平的第三电平上制造铜电感器 水平。 电容器有铝板。 根据另一个实施例，在基板上方的第一电平中制造电阻器，在垂直于第一电平的第二电平上制造铜电感器，并且制造在垂直于第二电平的第三电平的电容器 水平。 电容器可以具有铝板，或者铜电感器的一部分可以用作其板之一。

公开(公告)号：US07276441B1

公开(公告)日：2007-10-02

申请号：US10414601

申请日：2003-04-15

申请人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

发明人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

IPC分类号： H01L21/44 ,  H01L29/40 ,  H01L23/532

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改善的对铜的粘合性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

公开(公告)号：US07115425B2

公开(公告)日：2006-10-03

申请号：US11072127

申请日：2005-03-04

申请人： Peter A. Burke ,  Eric J. Kirchner ,  James R. B. Elmer

发明人： Peter A. Burke ,  Eric J. Kirchner ,  James R. B. Elmer

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L21/31053

摘要： A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.

摘要翻译： 一种用于监测基板上的集成电路结构的抛光工艺参数的方法。 第一个计量站点被构建在基板上。 第一个测量站点代表了高密度集成电路结构的设计极限。 第一计量站点是通过在抛光停止材料的相对大的表面区域内放置相对较小的水平表面区域沟槽而形成的。 第二个计量站点也在基板上构建。 第二个测量站点是低密度集成电路结构的设计极限。 第二计量站点通过在抛光停止材料的相对小的表面区域内放置相对较大的水平表面区域沟槽而形成。 衬底被绝缘材料层覆盖，从而至少填充沟槽。 计算出将沟槽基本上填充到抛光停止材料领域的顶表面所需的绝缘材料的目标厚度。 抛光衬底直到第一测量点的沟槽中的绝缘材料的第一厚度不超过目标厚度。 测量第二测量位置的沟槽中的绝缘材料的第二厚度，并且监测基于第一厚度和第二厚度的值作为用于集成电路结构的抛光工艺参数。

公开(公告)号：US06905909B2

公开(公告)日：2005-06-14

申请号：US10691400

申请日：2003-10-22

申请人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

发明人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

IPC分类号： C23C16/32 ,  H01L21/00 ,  H01L21/314 ,  H01L21/46 ,  H01L21/768 ,  H01L29/15

CPC分类号： H01L21/02167 ,  C23C16/325 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76828

摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

摘要翻译： 在基底上形成基本上无氧的碳化硅层的方法，其中碳化硅层的介电常数小于约4。 基板保持在约零摄氏度和约百摄氏度之间的沉积温度，并且以不超过约一千科学立方厘米每分钟的速率引入四甲基硅烷的气流。 沉积压力保持在约1毫乇至约100乇之间，并且以不大于约2千瓦的功率产生射频等离子体放电。 当形成所需的碳化硅层厚度时，等离子体放电停止。