公开(公告)号：USD365084S

公开(公告)日：1995-12-12

申请号：US26966

申请日：1994-08-10

Applicant: Edward D. Suski ,  David J. Silva ,  Glenn G. Miner

Designer： Edward D. Suski ,  David J. Silva ,  Glenn G. Miner

公开(公告)号：US5414223A

公开(公告)日：1995-05-09

申请号：US288470

申请日：1994-08-10

Applicant: Edward D. Suski ,  David J. Silva ,  Glenn G. Miner

Inventor： Edward D. Suski ,  David J. Silva ,  Glenn G. Miner

IPC: H05K1/11 ,  H05K3/32 ,  H05K3/34 ,  H05K3/42 ,  H05K1/02

CPC classification number: H05K1/0215 ,  H05K1/115 ,  H05K1/116 ,  H05K2201/0979 ,  H05K2201/10409 ,  H05K2203/044 ,  H05K3/325 ,  H05K3/3452 ,  H05K3/3468 ,  H05K3/429

Abstract: An improved omni-directional non-occluding solder pad design for printed circuit boards comprising a plurality of spokes radiating outward from a through-hole on the printed circuit board, with a ring concentric to the through-hole that intersects each of the plurality of spokes at approximately a perpendicular angle. The ringed-spoke configuration eliminates the need to ensure proper orientation of the solder pad on the printed circuit board prior to a wave soldering process since the symmetrical ringed-spoke design is omni-directional. The concentric ring structure provides an additional contact area of solder between the printed circuit board and a computer chassis. This additional contact area of solder ensures that there is a sufficient electrical connection between the printed circuit board and the computer chassis such that when the printed circuit board is mounted to the computer chassis, a proper grounding connection is provided.

Abstract translation: 一种用于印刷电路板的改进的全向非阻塞焊盘设计，包括从印刷电路板上的通孔向外辐射的多个辐条，其中与通孔相同的环与多个辐条中的每一个相交 大致垂直的角度。 环形轮辐配置无需在波峰焊工艺之前确保焊盘在印刷电路板上的正确定位，因为对称环形辐条设计是全方位的。 同心环结构在印刷电路板和计算机机箱之间提供了焊料的附加接触区域。 这种附加的焊料接触区域确保了在印刷电路板和计算机机架之间存在足够的电连接，使得当印刷电路板安装到计算机机箱时，提供了适当的接地连接。

公开(公告)号：US5764488A

公开(公告)日：1998-06-09

申请号：US661617

申请日：1996-06-11

Applicant: David J. Silva ,  Mitchell G. Dorfmeyer

Inventor： David J. Silva ,  Mitchell G. Dorfmeyer

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/111 ,  H05K1/0295 ,  H05K1/0243 ,  H05K2201/09954 ,  H05K2201/1006 ,  Y02P70/611

Abstract: A printed circuit board having a footprint that is capable of receiving one of two electronic components having differing pin configurations. The footprint includes a first and a second common pin receptor arranged about a first axis. The first and second common pin receptors are configured to receive a first and a second pin on either of the electronic components. The footprint also includes a third pin receptor that is positioned along the first axis so as to be interposed between the first and the second common pin receptors and is configured to receive a third pin receptor of the first electronic component. The footprint also includes a fourth pin receptor that is positioned along a second axis, that is orthogonal to and intersects the first axis at the location of the third pin receptor. The fourth pin receptor is configured to receive a third pin of the second electronic component. In one embodiment, the electronic components are surface mount EMI filters and the third and fourth pin receptors are electrically connected. Hence, electronic components having three pins that have two different configurations can be accommodated in the same footprint.

Abstract translation: 一种印刷电路板，其具有能够接收具有不同引脚配置的两个电子部件中的一个的印迹。 占地面积包括围绕第一轴布置的第一和第二公共销接收体。 第一和第二公共引脚接收器被配置为在任一电子部件上接收第一引脚和第二引脚。 脚印还包括沿着第一轴定位的第三针式接收器，以便插入在第一和第二公共针式接收器之间，并且被配置为接收第一电子部件的第三针式接收器。 脚印还包括沿第二轴定位的第四针接收器，其在第三针接收器的位置处与第一轴正交并与之相交。 第四针接收器被配置为接收第二电子部件的第三引脚。 在一个实施例中，电子部件是表面贴装EMI滤波器，并且第三和第四针式接收器电连接。 因此，具有三个具有两个不同配置的引脚的电子部件可以容纳在相同的占用空间中。

公开(公告)号：US5751557A

公开(公告)日：1998-05-12

申请号：US667617

申请日：1996-06-21

Applicant: David J. Silva

Inventor： David J. Silva

IPC: H01R12/55 ,  H01R29/00 ,  H05K1/00 ,  H05K1/11 ,  H05K3/34 ,  H01R9/09

CPC classification number: H05K1/111 ,  H05K1/0295 ,  H05K2201/09954 ,  H05K2201/10689 ,  H05K3/3421 ,  Y02P70/611

Abstract: A printed circuit board has a first plurality of pin receptors configured to receive a first type of SRAM memory device, a second plurality of pin receptors configured to receive a second type of SRAM memory device and a third plurality of pin receptors configured to receive a third type of SRAM memory device. The first plurality of pin receptors are formed in two parallel lines that extend in a first direction and define a portion of the boundary of a first area of the printed circuit board. The second and third pluralities of pin receptors are formed in the first area of the printed circuit board, with said second and third pluralities of pin receptors each comprising two parallel lines of pin receptors extending in a second direction, substantially orthogonal to the first direction. Conductive traces are formed between corresponding pin receptors in the first, second and third pluralities of pin receptors to thereby allow one of three different types of SRAM memory devices to be positioned on the footprint wherein the footprint occupies only the first area of the printed circuit board.

Abstract translation: 印刷电路板具有被配置为接收第一类型的SRAM存储器件的第一多个引脚接收器，被配置为接收第二类型的SRAM存储器件的第二多个引脚接收器和被配置为接收第三类型的第三种 类型的SRAM存储器件。 第一组多个针式接收器形成为沿着第一方向延伸并且限定印刷电路板的第一区域的边界的一部分的两条平行线。 第二和第三多个针式接收器形成在印刷电路板的第一区域中，其中所述第二和第三多个针式接收器分别包括两条平行的针式接收线，其沿第二方向延伸，基本上与第一方向正交。 导电迹线形成在第一，第二和第三多个针式接收器中的相应引脚接收器之间，从而允许三种不同类型的SRAM存储器件中的一种位于占位面积上，其中占位面积仅占据印刷电路板的第一区域 。

公开(公告)号：US5682297A

公开(公告)日：1997-10-28

申请号：US615155

申请日：1996-03-12

Applicant: David J. Silva

Inventor： David J. Silva

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/111 ,  H05K1/0295 ,  H05K1/0206 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09954 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10704 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A dual footprint for servicing either of two types of microprocessor packaging systems. A first footprint capable of receiving and servicing a first type of microprocessor packaging system, for example, a tape carrier package microprocessor package, is formed within a second footprint capable of receiving and servicing a second type of microprocessor packaging system, for example, a pin grid array microprocessor package. In a preferred form, the two footprints are electrically interconnected and the first footprint is offset by a selected angle from the second footprint to allow increased connectivity between the two footprints.

Abstract translation: 用于维护两种微处理器封装系统中的任一种的双重封装。 能够接收和维护第一类型的微处理器封装系统（例如，载带封装微处理器封装）的第一覆盖区形成在能够接收和维护第二类微处理器封装系统的第二覆盖区内，例如，引脚 网格阵列微处理器封装。 在优选形式中，两个覆盖区是电互连的，并且第一覆盖区从第二覆盖区偏移选定的角度以允许两个覆盖区之间的连接增加。

公开(公告)号：US5557505A

公开(公告)日：1996-09-17

申请号：US278798

申请日：1994-07-22

Applicant: David J. Silva

Inventor： David J. Silva

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/111 ,  H05K1/0295 ,  H05K1/0206 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09954 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10704 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A dual footprint for servicing either of two types of microprocessor packaging systems. A first footprint capable of receiving and servicing a first type of microprocessor packaging system, for example, a tape carrier package microprocessor package, is formed within a second footprint capable of receiving and servicing a second type of microprocessor packaging system, for example, a pin grid array microprocessor package. In a preferred form, the two footprints are electrically interconnected and the first footprint is offset by a selected angle from the second footprint to allow increased connectivity between the two footprints.

Abstract translation: 用于维护两种微处理器封装系统中的任一种的双重封装。 能够接收和维护第一类型的微处理器封装系统（例如，载带封装微处理器封装）的第一覆盖区形成在能够接收和维护第二类微处理器封装系统的第二覆盖区内，例如，引脚 网格阵列微处理器封装。 在优选形式中，两个覆盖区是电互连的，并且第一覆盖区从第二覆盖区偏移选定的角度以允许两个覆盖区之间的连接增加。