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公开(公告)号：US07423247B2
公开(公告)日：2008-09-09
申请号：US11626302
申请日：2007-01-23
申请人： David Kunst , Steven Martinez , Robert James Lewandowski , Peter Chambers , Joseph James Judkins , Luis Torres , Thomas A. Lindsay
发明人： David Kunst , Steven Martinez , Robert James Lewandowski , Peter Chambers , Joseph James Judkins , Luis Torres , Thomas A. Lindsay
CPC分类号： H01S5/0683 , H01S5/0617 , H01S5/06804 , H01S5/06808
摘要： An automatic power control system provides a control signal that regulates the output power of at least one laser diode. Coarse adjustment of the control signal is provided by a first means, preferably a digital variable resistor, while fine adjustment and compensation is provided by a second means, preferably by a digital-to-analog converter that receives an input signal proportional to a sensed control system parameter. The control system includes an operational amplifier having a first input coupled to sense output power, and a second input coupled to a DAC to provide finer resolution control. Memory can store system parameter or system parameter variations that can be coupled to the DAC and/or variable resistor to enhance system stability over ambient variations.
摘要翻译： 自动功率控制系统提供调节至少一个激光二极管的输出功率的控制信号。 控制信号的粗调是由第一装置，优选数字可变电阻器提供的，而微调和补偿由第二装置提供，优选地由接收与感测控制成正比的输入信号的数 - 模转换器 系统参数。 控制系统包括运算放大器，其具有耦合以感测输出功率的第一输入，以及耦合到DAC的第二输入以提供更精细的分辨率控制。 存储器可以存储可耦合到DAC和/或可变电阻器的系统参数或系统参数变化，以增强系统在环境变化方面的稳定性。
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公开(公告)号：US07166826B1
公开(公告)日：2007-01-23
申请号：US10294469
申请日：2002-11-13
申请人： David Kunst , Steven Martinez , Robert James Lewandowski , Peter Chambers , Joseph James Judkins, III , Luis Torres , Tom Lindsay
发明人： David Kunst , Steven Martinez , Robert James Lewandowski , Peter Chambers , Joseph James Judkins, III , Luis Torres , Tom Lindsay
CPC分类号： H01S5/0683 , H01S5/0617 , H01S5/06804 , H01S5/06808
摘要： An automatic power control system provides a control signal that regulates the output power of at least one laser diode. Coarse adjustment of the control signal is provided by a first means, preferably a digital variable resistor, while fine adjustment and compensation is provided by a second means, preferably by a digital-to-analog converter that receives an input signal proportional to a sensed control system parameter. The control system includes an operational amplifier having a first input coupled to sense output power, and a second input coupled to a DAC to provide finer resolution control. Memory can store system parameter or system parameter variations that can be coupled to the DAC and/or variable resistor to enhance system stability over ambient variations.
摘要翻译： 自动功率控制系统提供调节至少一个激光二极管的输出功率的控制信号。 控制信号的粗调是由第一装置，优选数字可变电阻器提供的，而微调和补偿由第二装置提供，优选地由接收与感测控制成正比的输入信号的数 - 模转换器 系统参数。 控制系统包括运算放大器，其具有耦合以感测输出功率的第一输入，以及耦合到DAC的第二输入以提供更精细的分辨率控制。 存储器可以存储可耦合到DAC和/或可变电阻器的系统参数或系统参数变化，以增强系统在环境变化方面的稳定性。
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公开(公告)号：US20070114361A1
公开(公告)日：2007-05-24
申请号：US11626302
申请日：2007-01-23
申请人： David Kunst , Steven Martinez , Robert Lewandowski , Peter Chambers , Joseph Judkins , Luis Torres , Tom Lindsay
发明人： David Kunst , Steven Martinez , Robert Lewandowski , Peter Chambers , Joseph Judkins , Luis Torres , Tom Lindsay
IPC分类号： G01J1/32
CPC分类号： H01S5/0683 , H01S5/0617 , H01S5/06804 , H01S5/06808
摘要： An automatic power control system provides a control signal that regulates the output power of at least one laser diode. Coarse adjustment of the control signal is provided by a first means, preferably a digital variable resistor, while fine adjustment and compensation is provided by a second means, preferably by a digital-to-analog converter that receives an input signal proportional to a sensed control system parameter. The control system includes an operational amplifier having a first input coupled to sense output power, and a second input coupled to a DAC to provide finer resolution control. Memory can store system parameter or system parameter variations that can be coupled to the DAC and/or variable resistor to enhance system stability over ambient variations.
摘要翻译： 自动功率控制系统提供调节至少一个激光二极管的输出功率的控制信号。 控制信号的粗调是由第一装置，优选数字可变电阻器提供的，而微调和补偿由第二装置提供，优选地由接收与感测控制成正比的输入信号的数 - 模转换器 系统参数。 控制系统包括运算放大器，其具有耦合以感测输出功率的第一输入，以及耦合到DAC的第二输入以提供更精细的分辨率控制。 存储器可以存储可耦合到DAC和/或可变电阻器的系统参数或系统参数变化，以增强系统在环境变化方面的稳定性。
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4.发明授权公开(公告)号：US07370069B2
公开(公告)日：2008-05-06
申请号：US10759786
申请日：2004-01-15
IPC分类号： G06F15/00
CPC分类号： G06F1/0356
摘要： A device for performing numerical value conversion of a digital input value in a first unit to a second unit being a natural unit includes a look-up table storing an array of coefficients for performing the numerical value conversion. The look-up table is indexed using a first parameter to provide a selected coefficient. An arithmetic logic unit (ALU) is coupled to receive the digital input value and the selected coefficient and perform the numerical value conversion based on a first equation using the selected coefficient to compute a digital output value in the second unit. The first unit can be an arbitrary ADC unit and the second unit is a natural unit of physical measurement, such as volts, amperes, degree Centigrade. Furthermore, the device can be used to perform numerical value conversion from the arbitrary unit to the natural unit having a linear or a non-linear relationship.
摘要翻译： 用于将第一单元中的数字输入值数值转换为作为自然单元的第二单元的设备包括存储执行数值转换的系数阵列的查找表。 使用第一参数来索引查找表以提供所选择的系数。 耦合算术逻辑单元（ALU）以接收数字输入值和所选择的系数，并且使用所选择的系数基于第一等式执行数值转换，以计算第二单元中的数字输出值。 第一个单元可以是任意的ADC单元，第二个单元是物理测量的自然单位，如伏特，安培，摄氏度。 此外，该装置可以用于执行从任意单元到具有线性或非线性关系的自然单元的数值转换。
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5.发明授权Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands 有权使用饱和限制运算逻辑单元支持可变分辨率操作数的数值转换公开(公告)号：US07395287B2
公开(公告)日：2008-07-01
申请号：US10759988
申请日：2004-01-15
IPC分类号： G06F15/00
CPC分类号： H03M1/1235 , H03M1/129
摘要： A device for performing numerical value conversion of a digital input value in a first unit to a second, natural unit where the digital input value is a digitized value of a first measurement parameter includes a look-up table storing an array of coefficients for performing the numerical value conversion for multiple measurement parameters. The look-up table is indexed using a first parameter indicative of the first measurement parameter to provide a selected coefficient. The device further includes an arithmetic logic unit (ALU) receiving the digital input value and the selected coefficient and performing the numerical value conversion based on a first equation and the selected coefficient to compute a digital output value. The device also includes a saturation-limit circuit coupled to receive the digital output value from the arithmetic logic unit and provide a predetermined output value when the digital output value exceeds a predetermined maximum value.
摘要翻译： 一种用于对第一单元中的数字输入值进行数值转换的装置，其中数字输入值是第一测量参数的数字化值的第二自然单元包括：存储用于执行第一测量参数的系数阵列的查找表; 多个测量参数的数值转换。 使用指示第一测量参数的第一参数来索引查找表以提供所选择的系数。 该装置还包括接收数字输入值和所选系数的算术逻辑单元（ALU），并且基于第一方程和所选择的系数执行数值转换以计算数字输出值。 该装置还包括饱和极限电路，其被耦合以从所述算术逻辑单元接收所述数字输出值，并且当所述数字输出值超过预定最大值时提供预定的输出值。
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公开(公告)号：US20070139076A1
公开(公告)日：2007-06-21
申请号：US11676070
申请日：2007-02-16
申请人： Peter Chambers
发明人： Peter Chambers
IPC分类号： H03K19/00
CPC分类号： H03K19/1731 , H01L2224/49113
摘要： A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.
摘要翻译： 一种耦合到包括输入缓冲器，输出缓冲器和焊盘管理电路的集成电路中的输入 - 输出接合焊盘（I / O焊盘）的电路。 焊盘管理电路接收第一数据信号，第一输出使能信号和表示I / O焊盘的连接状态的配置信号，并产生第二数据信号和第二输出使能信号。 当配置信号指示将I / O焊盘连接到封装引脚时，焊盘管理电路将第一数据信号作为第二数据信号耦合，并将第一输出使能信号耦合作为第二输出使能信号。 当配置信号指示I / O焊盘不连接时，焊盘管理电路确定第二输出使能信号并产生具有预定值的第二数据信号。
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7.发明申请Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands 有权使用饱和限制运算逻辑单元支持可变分辨率操作数的数值转换公开(公告)号：US20050131973A1
公开(公告)日：2005-06-16
申请号：US10759988
申请日：2004-01-15
申请人： Peter Chambers , Joseph Judkins
发明人： Peter Chambers , Joseph Judkins
IPC分类号： G06F7/00
CPC分类号： H03M1/1235 , H03M1/129
摘要： A device for performing numerical value conversion of a digital input value in a first unit to a second, natural unit where the digital input value is a digitized value of a first measurement parameter includes a look-up table storing an array of coefficients for performing the numerical value conversion for multiple measurement parameters. The look-up table is indexed using a first parameter indicative of the first measurement parameter to provide a selected coefficient. The device further includes an arithmetic logic unit (ALU) receiving the digital input value and the selected coefficient and performing the numerical value conversion based on a first equation and the selected coefficient to compute a digital output value. The device also includes a saturation-limit circuit coupled to receive the digital output value from the arithmetic logic unit and provide a predetermined output value when the digital output value exceeds a predetermined maximum value.
摘要翻译： 一种用于对第一单元中的数字输入值进行数值转换的装置，其中数字输入值是第一测量参数的数字化值的第二自然单元包括：存储用于执行第一测量参数的系数阵列的查找表; 多个测量参数的数值转换。 使用指示第一测量参数的第一参数来索引查找表以提供所选择的系数。 该装置还包括接收数字输入值和所选系数的算术逻辑单元（ALU），并且基于第一方程和所选择的系数执行数值转换以计算数字输出值。 该装置还包括饱和极限电路，其被耦合以从所述算术逻辑单元接收所述数字输出值，并且当所述数字输出值超过预定最大值时提供预定的输出值。
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公开(公告)号：US06898680B2
公开(公告)日：2005-05-24
申请号：US10336296
申请日：2003-01-03
申请人： Peter Chambers
发明人： Peter Chambers
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C16/349
摘要： A method and structure are provided that reduce the overall time of the read-erase-modify-write cycle time of non-volatile memories. Specifically, the erase operation of the read-erase-write cycle is avoided in certain circumstances. In one embodiment, the erase operation is skipped where a predetermined pattern is found in at least a portion the block. In another embodiment, the erase operation is skipped where a status of the block indicates that the erase operation can be skipped.
摘要翻译： 提供了减少非易失性存储器的读擦除修改 - 写周期时间的总时间的方法和结构。 具体地说，在某些情况下避免了擦写写周期的擦除操作。 在一个实施例中，擦除操作被跳过，其中在块的至少一部分中发现预定模式。 在另一个实施例中，跳过擦除操作，其中块的状态指示可以跳过擦除操作。
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9.发明授权Optimizing the performance of asynchronous bus bridges with dynamic transactions 有权通过动态事务优化异步总线桥的性能公开(公告)号：US06289406B1
公开(公告)日：2001-09-11
申请号：US09187325
申请日：1998-11-06
IPC分类号： G06F1314
CPC分类号： G06F13/4027
摘要： A system and method for completing a read transaction between an initiator device and a host memory device in a computer system, in which the present invention optimizes the retry behavior of the initiator device and a target device. The system of the present invention includes a bus bridge device, wherein the bus bridge device includes a target device coupled to the initiator device via a bus; the host memory device coupled to the bus bridge device; and a timer mechanism coupled to the target device. The initiator device is adapted to initiate a present read transaction via the target device, such that an access is asserted between the initiator device and the target device. The timer mechanism is adapted to measure target latency for one or more read transactions preceding the present read transaction, and the timer mechanism is further adapted to use the target latency to calculate a dynamic target latency period. The target device is adapted to maintain the access to the initiator device during the dynamic target latency period. Thus, in accordance with the present invention, the target latency is dynamically measured and used to optimize the retry behavior of the initiator and target devices.
摘要翻译： 一种用于完成计算机系统中的发起者设备和主机存储设备之间的读取事务的系统和方法，其中本发明优化了发起者设备和目标设备的重试行为。 本发明的系统包括总线桥装置，其中总线桥装置包括经由总线耦合到启动器装置的目标装置; 主机存储设备耦合到总线桥接器件; 以及耦合到目标设备的定时器机构。 启动器设备适于经由目标设备发起当前读取事务，使得在发起者设备和目标设备之间确认访问。 定时器机构适于测量当前读取事务之前的一个或多个读取事务的目标延迟，并且定时器机制还适于使用目标等待时间来计算动态目标等待时间周期。 目标设备适于在动态目标潜伏期期间维持对发起者设备的访问。 因此，根据本发明，动态测量目标延迟并用于优化发起者和目标设备的重试行为。
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10.发明授权Virtual contiguous FIFO for combining multiple data packets into a single contiguous stream 失效用于将多个数据分组组合成单个连续流的虚拟连续FIFO
公开(公告)号：US6016315A
公开(公告)日：2000-01-18
申请号：US846294
申请日：1997-04-30
申请人： Peter Chambers , Scott E. Harrow
发明人： Peter Chambers , Scott E. Harrow
CPC分类号： H04L49/90
摘要： A virtual contiguous system for combining multiple and arbitrarily-sized and aligned digital data packets from a PCI bus to a DSP circuit is disclosed. Information from the PCI bus is supplied directly to a plurality of FIFO RAM memory units. Each packet of digital data includes data packet descriptors identifying at least the start address for each data packet and the size of each data packet. The system utilizes this information to operate a read pointer and a write pointer to remove data from the FIFO RAM memory units on a sequential bit-by-bit basis and to supply said data packets to said RAM memory units by means of a write pointer operated by said control circuit. The information transfer is managed on the read side of the FIFO RAM memory units with minimal processing on the write side.
摘要翻译： 公开了一种虚拟连续系统，用于将来自PCI总线的多个和任意大小和对准的数字数据分组组合到DSP电路。 来自PCI总线的信息被直接提供给多个FIFO RAM存储器单元。 每个数字数据包包括至少标识每个数据包的起始地址和每个数据包的大小的数据包描述符。 系统利用该信息来操作读指针和写指针，以逐位逐位地从FIFO RAM存储器单元中移除数据，并通过写指针来将所述数据分组提供给所述RAM存储器单元 由所述控制电路。 信息传输在FIFO RAM存储器单元的读取端以最小的写入侧处理来管理。
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