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    Programmable logic device architectures and methods for implementing logic in those architectures
    5.
    发明授权
    Programmable logic device architectures and methods for implementing logic in those architectures 有权
    可编程逻辑器件架构和方法，用于在这些架构中实现逻辑

    公开(公告)号：US07716623B1

    公开(公告)日：2010-05-11

    申请号：US12580038

    申请日：2009-10-15

    申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    IPC分类号： H03K17/693

    CPC分类号： H03K19/17736

    摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

    摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LAB）“的群集在一起的逻辑元件（”LE“）。 为了节省面积，与现有技术相比，减少或消除了局部反馈资源（用于将LAB中的LE的输出反馈到LAB中的LE的输入）。 因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须通过LAB的通用输入路由资源路由，所以保存那些 资源。 例如，通过在确定在LAB中一起实现哪些逻辑功能时，更重要的是找到具有共同输入的逻辑功能。

    Programmable logic device architectures and methods for implementing logic in those architectures
    6.
    发明授权
    Programmable logic device architectures and methods for implementing logic in those architectures 有权
    可编程逻辑器件架构和方法，用于在这些架构中实现逻辑

    公开(公告)号：US07619443B1

    公开(公告)日：2009-11-17

    申请号：US11356762

    申请日：2006-02-16

    申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

    摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LABs“）的集群在一起的逻辑元件（”LE“）。为了保存区域，本地反馈资源（用于将LAB中的LE的输出馈送回到 与现有技术相比，减少或消除了LAB中的LE的输入），因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须是 通过LAB的通用输入路由资源路由，重要的是保存这些资源，例如，通过更加重视找到具有共同输入的逻辑功能，在决定在 劳顾会

    Organizations of logic modules in programmable logic devices
    7.
    发明授权
    Organizations of logic modules in programmable logic devices 有权
    可编程逻辑器件中逻辑模块的组织

    公开(公告)号：US07176718B1

    公开(公告)日：2007-02-13

    申请号：US11040457

    申请日：2005-01-21

    申请人： Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    发明人： Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728

    摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

    摘要翻译： 在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。 这种分组中的逻辑元素被划分为至少两个子组。 提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。 可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用 比对方。

    Organizations of logic modules in programmable logic devices
    8.
    发明授权
    Organizations of logic modules in programmable logic devices 有权
    可编程逻辑器件中逻辑模块的组织

    公开(公告)号：US07368944B1

    公开(公告)日：2008-05-06

    申请号：US11649748

    申请日：2007-01-03

    申请人： Michael D. Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    发明人： Michael D. Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728

    摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

    摘要翻译： 在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。 这种分组中的逻辑元素被划分为至少两个子组。 提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。 可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用 比对方。

    Caching technique for electrical simulation of VLSI interconnect
    9.
    发明授权
    Caching technique for electrical simulation of VLSI interconnect 失效
    VLSI互连电气仿真缓存技术

    公开(公告)号：US07693700B1

    公开(公告)日：2010-04-06

    申请号：US10462031

    申请日：2003-06-13

    申请人： Tim Vanderhoek ,  David Lewis

    发明人： Tim Vanderhoek ,  David Lewis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F2217/82

    摘要： Circuits, methods, and apparatus for including interconnect parasitics without greatly increasing circuit simulation complexity and run times. Interconnect paths are reduced to one of a number of simplified topologies based on path width, length, or other parameters. The input drive waveform is similarly approximated. A grid array is formed in advance, where each point in the grid array corresponds to a set of values relating to a path topology, input waveform, and resulting output waveform. The simplified interconnect path and input waveform are mapped into a set of parameters which corresponds to a location in the predetermined grid array. The output waveform is determined by interpolating output waveforms from gridpoints surrounding the location.

    摘要翻译： 包括互连寄生效应的电路，方法和设备，而不会大大增加电路仿真的复杂性和运行时间。 基于路径宽度，长度或其他参数，互连路径减少到许多简化拓扑之一。 输入驱动波形类似地近似。 预先形成网格阵列，其中网格阵列中的每个点对应于与路径拓扑，输入波形和所得到的输出波形相关的一组值。 简化的互连路径和输入波形被映射到对应于预定网格阵列中的位置的一组参数中。 输出波形通过从位置周围的网格点内插输出波形来确定。