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    Memory elements with increased write margin and soft error upset immunity
    5.
    发明授权
    Memory elements with increased write margin and soft error upset immunity 有权
    存储器元件具有增加的写入裕度和软错误失真的抗扰度

    公开(公告)号：US08711614B1

    公开(公告)日：2014-04-29

    申请号：US13052374

    申请日：2011-03-21

    申请人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

    发明人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

    IPC分类号： G11C11/34

    CPC分类号： G11C8/10

    摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

    摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。 晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。 可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。 在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。

    Memory elements with increased write margin and soft error upset immunity
    6.
    发明授权
    Memory elements with increased write margin and soft error upset immunity 有权
    存储器元件具有增加的写入裕度和软错误失真的抗扰度

    公开(公告)号：US07920410B1

    公开(公告)日：2011-04-05

    申请号：US12391230

    申请日：2009-02-23

    申请人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

    发明人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

    IPC分类号： G11C11/00 ,  G11C5/06

    CPC分类号： G11C8/10

    摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

    摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。 晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。 可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。 在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。

    Integrated circuits with asymmetric and stacked transistors
    7.
    发明授权
    Integrated circuits with asymmetric and stacked transistors 有权
    具有不对称和堆叠晶体管的集成电路

    公开(公告)号：US08482963B1

    公开(公告)日：2013-07-09

    申请号：US12629831

    申请日：2009-12-02

    申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

    摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

    Testing circuitry for programmable logic devices with selectable power supply voltages
    8.
    发明授权
    Testing circuitry for programmable logic devices with selectable power supply voltages 有权
    具有可选电源电压的可编程逻辑器件的测试电路

    公开(公告)号：US07571413B1

    公开(公告)日：2009-08-04

    申请号：US11478148

    申请日：2006-06-28

    申请人： Jayabrata Ghosh Dastidar ,  Srinivas Perisetty ,  Andy L. Lee

    发明人： Jayabrata Ghosh Dastidar ,  Srinivas Perisetty ,  Andy L. Lee

    IPC分类号： G06F17/50 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G01R31/318516 ,  G01R31/318575 ,  H03K19/17744 ,  H03K19/17784

    摘要： A programmable integrated circuit has multiple power supply voltages. Power supply voltages are distributed using power supply distribution lines. The integrated circuit has programmable power supply voltage selection switches. Each power supply voltage selection switch has its inputs connected to the power supply distribution lines and supplies a selected power supply voltage to a circuit block at its output. Test circuits are provided for testing the power supply voltage selection switches. During testing, the power supply voltage selection switches are adjusted to produce various power supply voltages at their outputs. The test circuit associated with each switch performs voltage comparisons to determine whether the switch is functioning properly. Each test circuit produces a test result based on its voltage comparison. The test results from the test circuits are provided to a scan chain, which unloads the test results from the integrated circuit to a tester for analysis.

    摘要翻译： 可编程集成电路具有多个电源电压。 使用电源配电线分配电源电压。 集成电路具有可编程电源电压选择开关。 每个电源电压选择开关的输入连接到电源配线，并将选定的电源电压提供给其输出端的电路块。 提供测试电路用于测试电源电压选择开关。 在测试期间，调整电源电压选择开关，以在其输出端产生各种电源电压。 与每个开关相关的测试电路执行电压比较，以确定开关是否正常工作。 每个测试电路基于其电压比较产生测试结果。 将测试电路的测试结果提供给扫描链，该扫描链将测试结果从集成电路卸载到测试仪进行分析。

    Memory elements with voltage overstress protection
    9.
    发明授权
    Memory elements with voltage overstress protection 有权
    具有电压过载保护功能的存储器元件

    公开(公告)号：US08369175B1

    公开(公告)日：2013-02-05

    申请号：US12874152

    申请日：2010-09-01

    申请人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

    发明人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

    IPC分类号： G11C5/14

    CPC分类号： G11C11/412 ,  G11C15/04

    摘要： Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

    摘要翻译： 集成电路可以包括具有电压过应力保护的存储器元件。 存储单元的一种合适布置可以包括具有两个交叉耦合的反相器的锁存器。 两个交叉耦合反相器中的每一个可以耦合在第一和第二电源线之间，并且可以包括具有连接到单独的电源线的栅极的晶体管。 另一种合适的存储单元布置可以包括三个交叉耦合电路。 三个电路中的两个可以由第一正电源线供电，而剩余电路可以由第二正电源线供电。 这些存储单元可用于向对应的通道提供升高的正静态控制信号和降低的地面静态控制信号。 这些存储单元可以包括在读/写操作期间使用的存取晶体管和读缓冲电路。

    ESD protection structure
    10.
    发明授权
    ESD protection structure 失效
    ESD保护结构

    公开(公告)号：US07511932B1

    公开(公告)日：2009-03-31

    申请号：US11836700

    申请日：2007-08-09

    申请人： Antonio Gallerano ,  Jeffrey T. Watt ,  Srinivas Perisetty ,  Cheng-Hsiung Huang

    发明人： Antonio Gallerano ,  Jeffrey T. Watt ,  Srinivas Perisetty ,  Cheng-Hsiung Huang

    IPC分类号： H02H9/00 ,  H02H1/00

    CPC分类号： H01L27/0266

    摘要： The present invention is an ESD protection circuit that discharges both positive and negative electrostatic events. A preferred embodiment of the circuit comprises a first NMOS transistor having a source and drain connected between ground and an I/O pad and second and third NMOS transistors and a resistor connected in series between ground and the I/O pad. The gate and body of the first transistor and the bodies of the second and third transistors are connected to a node between the second and third transistors; the gate of the second transistor is connected to the I/O pad through a second resistor; and the gate of the third transistor is connected to ground. The second and third transistors maintain the gate and body voltage of the first transistor at the pad voltage when the pad experiences negative voltages and at ground voltage when the pad experiences positive voltages. As a result, the first transistor can discharge both negative and positive ESC events through parasitic bipolar conduction, without any additional circuits such as diodes used either to stop leakage currents or to conduct ESD current.

    摘要翻译： 本发明是放电正静电事件和负静电事件两者的ESD保护电路。 电路的优选实施例包括第一NMOS晶体管，其源极和漏极连接在地与I / O焊盘之间，第二和第三NMOS晶体管和电阻串联连接在地和I / O焊盘之间。 第一晶体管的栅极和主体以及第二和第三晶体管的主体连接到第二和第三晶体管之间的节点; 第二晶体管的栅极通过第二电阻器连接到I / O焊盘; 并且第三晶体管的栅极连接到地。 当焊盘经受负电压时，第二晶体管和第三晶体管的栅极和体电压保持在焊盘电压，并且当焊盘经受正电压时，其保持接地电压。 因此，第一晶体管可以通过寄生双极导通来放电负和正的ESC事件，而不需要任何额外的电路，例如用于阻止漏电流或导通ESD电流的二极管。