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    Programmable logic device architectures and methods for implementing logic in those architectures
    2.
    发明授权
    Programmable logic device architectures and methods for implementing logic in those architectures 有权
    可编程逻辑器件架构和方法，用于在这些架构中实现逻辑

    公开(公告)号：US07716623B1

    公开(公告)日：2010-05-11

    申请号：US12580038

    申请日：2009-10-15

    申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    IPC分类号： H03K17/693

    CPC分类号： H03K19/17736

    摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

    摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LAB）“的群集在一起的逻辑元件（”LE“）。 为了节省面积，与现有技术相比，减少或消除了局部反馈资源（用于将LAB中的LE的输出反馈到LAB中的LE的输入）。 因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须通过LAB的通用输入路由资源路由，所以保存那些 资源。 例如，通过在确定在LAB中一起实现哪些逻辑功能时，更重要的是找到具有共同输入的逻辑功能。

    Organizations of logic modules in programmable logic devices
    4.
    发明授权
    Organizations of logic modules in programmable logic devices 有权
    可编程逻辑器件中逻辑模块的组织

    公开(公告)号：US07176718B1

    公开(公告)日：2007-02-13

    申请号：US11040457

    申请日：2005-01-21

    申请人： Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    发明人： Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728

    摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

    摘要翻译： 在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。 这种分组中的逻辑元素被划分为至少两个子组。 提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。 可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用 比对方。

    Organizations of logic modules in programmable logic devices
    6.
    发明授权
    Organizations of logic modules in programmable logic devices 有权
    可编程逻辑器件中逻辑模块的组织

    公开(公告)号：US07368944B1

    公开(公告)日：2008-05-06

    申请号：US11649748

    申请日：2007-01-03

    申请人： Michael D. Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    发明人： Michael D. Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728

    摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

    摘要翻译： 在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。 这种分组中的逻辑元素被划分为至少两个子组。 提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。 可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用 比对方。

    Asymmetric signal routing in a programmable logic device
    7.
    发明授权
    Asymmetric signal routing in a programmable logic device 有权
    可编程逻辑器件中的不对称信号路由

    公开(公告)号：US08643399B1

    公开(公告)日：2014-02-04

    申请号：US13229567

    申请日：2011-09-09

    申请人： Tim Vanderhoek ,  Michael Chan

    发明人： Tim Vanderhoek ,  Michael Chan

    IPC分类号： H01L25/00

    CPC分类号： H03K19/17744 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A programmable logic device includes an array of functional blocks and input/output elements disposed at the periphery of the programmable logic device. The programmable logic device also includes conductors configured to conduct signals between the functional blocks and between the functional blocks and the routing channels. The number of conductors that propagate signals in a direction toward the periphery and out of the array is greater than the number of conductors that propagate signals into the array in a direction away from the periphery.

    摘要翻译： 可编程逻辑器件包括布置在可编程逻辑器件的外围的功能块和输入/输出元件阵列。 可编程逻辑器件还包括被配置为在功能块之间以及功能块和路由通道之间传导信号的导体。 在朝向周边的方向和阵列之外传播信号的导体的数量大于沿远离周边的方向将信号传播到阵列中的导体的数量。

    Method and apparatus for performing delay annotation
    10.
    发明授权
    Method and apparatus for performing delay annotation 有权
    用于执行延迟注释的方法和装置

    公开(公告)号：US08661385B1

    公开(公告)日：2014-02-25

    申请号：US11899837

    申请日：2007-09-07

    申请人： Lyndon Francis Carvalho ,  Chris Wysocki ,  Tim Vanderhoek ,  Adrian Ludwin

    发明人： Lyndon Francis Carvalho ,  Chris Wysocki ,  Tim Vanderhoek ,  Adrian Ludwin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/82

    摘要： A method for designing a system on a target device includes performing delay annotation where a first delay associated with a first aspect of the system is determined by a first software thread and a second delay associated with a second aspect of the system is determined by a second software thread and the first and second software threads operate in parallel. Ensuring independence between each aspect of the system will facilitate efficient parallelism (i.e. minimal synchronization) while still maintaining serial equivalency.

    摘要翻译： 用于在目标设备上设计系统的方法包括执行延迟注释，其中与系统的第一方面相关联的第一延迟由第一软件线程确定，并且与系统的第二方面相关联的第二延迟由第二软件线程确定 软件线程和第一和第二软件线程并行运行。 确保系统的每个方面之间的独立性将有助于有效的并行性（即最小同步），同时仍保持串行等同性。