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公开(公告)号：US20120206181A1
公开(公告)日：2012-08-16
申请号：US13370784
申请日：2012-02-10
申请人： David Lin , Suresh Balasubramanian
发明人： David Lin , Suresh Balasubramanian
CPC分类号： H03L7/0816 , H03K5/135 , H03K5/14 , H03L7/08
摘要： A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.
摘要翻译： 延迟电路通过使用相同的物理延迟线对来提供正交延迟的选通脉冲，严格控制的正交DLL和写/读电平延迟线。 通过复用不同的使用模型，对多个延迟线的需求显着减少到每个字节仅两个延迟线。 因此，延迟电路在布局面积和功率方面提供了显着的节省。
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公开(公告)号：US09143140B2
公开(公告)日：2015-09-22
申请号：US13370784
申请日：2012-02-10
申请人： David Lin , Suresh Balasubramanian
发明人： David Lin , Suresh Balasubramanian
CPC分类号： H03L7/0816 , H03K5/135 , H03K5/14 , H03L7/08
摘要： A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.
摘要翻译： 延迟电路通过使用相同的物理延迟线对来提供正交延迟的选通脉冲，严格控制的正交DLL和写/读电平延迟线。 通过复用不同的使用模型，对多个延迟线的需求显着减少到每个字节仅两个延迟线。 因此，延迟电路在布局面积和功率方面提供了显着的节省。
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公开(公告)号：US09263151B2
公开(公告)日：2016-02-16
申请号：US13396824
申请日：2012-02-15
申请人： Thucydides Xanthopoulos , David Lin
发明人： Thucydides Xanthopoulos , David Lin
CPC分类号： G11C29/02 , G06F11/27 , G11C29/022 , G11C29/48
摘要： A memory interface enables AC characterization under test conditions without requiring the use of Automated Test Equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).
摘要翻译： 存储器接口可以在测试条件下实现AC特性，而无需使用自动测试设备（ATE）和功能模式。 存储器控制器可以被配置为通过测试接口生成输出模式，并且使用外部紧张眼随机数发生器和检验器创建用于输入规范测试的回送路径。 因此，可以通过测试接口（JTAG）在相对简单的测试设置和测试过程下评估存储器接口的电气和时序规范，而不是在自动测试中建立类似的存储器访问模式的复杂处理器程序 设备（ATE）。
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公开(公告)号：US20120004950A1
公开(公告)日：2012-01-05
申请号：US13174858
申请日：2011-07-01
申请人： Andrew Julian , Scott Julian , James Robertson , David Lin
发明人： Andrew Julian , Scott Julian , James Robertson , David Lin
CPC分类号： G06Q10/02 , G06Q30/0201 , G06Q30/0202 , G06Q30/0203 , G06Q30/0241
摘要： A method and system is presented for the integration of offline media tracking and measurement with an online audience validation system. In one embodiment, the system builds on the existing audience validation system functionality and enables advertisers and marketers to better track attendance and the consumption of offline media that is displayed at event for which tickets must be procured. In another embodiment, the system allows Advertisers and Marketers to track attendance and the exposure of ticket holders to specific media during the event and to subsequently use this information to target survey and offers to event attendees. In another embodiment, the ability to track online, mobile, and offline media affords the additional benefit to perform full conversion funnel tracking across those media that further enables CPA advertising as well.
摘要翻译： 提出了一种用于将离线媒体跟踪和测量与在线观众验证系统集成的方法和系统。 在一个实施例中，该系统建立在现有观众验证系统功能上，并且使得广告商和营销人员能够更好地跟踪在必须购买票据的事件中显示的离线媒体的出席率和消费。 在另一个实施例中，该系统允许广告商和营销人员在活动期间跟踪出席者和票持有者对特定媒体的曝光，并且随后使用该信息将调查和提供给活动参加者。 在另一个实施例中，跟踪在线，移动和离线媒体的能力提供了额外的优点，以便进一步实现CPA广告的这些媒体上的完全转换渠道跟踪。
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公开(公告)号：USD574328S1
公开(公告)日：2008-08-05
申请号：US29256524
申请日：2006-03-21
申请人： Caesar Chen , Donald Chen , David Lin , Greg Fournier
设计人： Caesar Chen , Donald Chen , David Lin , Greg Fournier
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公开(公告)号：US07227384B2
公开(公告)日：2007-06-05
申请号：US11201559
申请日：2005-08-11
申请人： Mondira Pant , Paul Gronowski , Randy Allmon , Manjunath Bhat , David Lin
发明人： Mondira Pant , Paul Gronowski , Randy Allmon , Manjunath Bhat , David Lin
IPC分类号： H03K19/20
CPC分类号： H03K19/0963 , G01R31/318572
摘要： A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.
摘要翻译： 用于将接收的多米诺骨牌逻辑信号转换成静态输出信号的电路包括一对逻辑门，其具有交叉耦合的输入和输出，并且响应于多米诺逻辑输入信号和时钟信号，以在定义的评估阶段期间锁存输入信号 通过时钟信号。 静态输出基于锁存值。 逻辑门之一是在扫描模式期间在静态输出处建立一个值的三态。 用于将接收到的静态逻辑信号转换为多米诺逻辑信号的电路包括响应于时钟信号的锁存器，以在预定义的时钟转换时锁存数据信号的值。 转换电路响应于时钟信号和数据信号的锁存值产生多米诺逻辑输出信号。 锁存器组件是三态的以在输出端建立一个值。
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