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公开(公告)号：US5822381A
公开(公告)日：1998-10-13
申请号：US435455
申请日：1995-05-05
CPC分类号： G06F1/10 , H04J3/0641
摘要： A clock system for a distributed multiprocessor system includes a plurality of local clock circuits and a distribution network. The distribution network includes a plurality of interconnected routers. Each local clock circuit is associated with a processing node of the multiprocessor system. Each local clock circuit generates a global clock source signal, provides the global clock source signal to the distribution network, receives a global clock signal back from the distribution network, and generates a global time value based on a local clock signal and the global clock signal. The router is part of the distribution network of the multiprocessor system. The router receives the global clock source signals from each of the local clock circuits, selects one of the global clock source signals as the global clock signal and provides the global clock signal to the distribution network for distribution to each of the local clock circuits.
摘要翻译： 用于分布式多处理器系统的时钟系统包括多个本地时钟电路和分配网络。 分配网络包括多个互连的路由器。 每个本地时钟电路与多处理器系统的处理节点相关联。 每个本地时钟电路产生全局时钟源信号，将全局时钟源信号提供给分配网络，从分配网络接收全局时钟信号，并根据本地时钟信号和全局时钟信号产生全局时间值 。 路由器是多处理器系统分发网络的一部分。 路由器接收来自每个本地时钟电路的全局时钟源信号，选择全局时钟源信号之一作为全局时钟信号，并将全局时钟信号提供给分配网络以分配给每个本地时钟电路。
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2.发明授权System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers 失效使用源时钟信号在通信网络中同步传输数据以将串行数据锁存到第一寄存器中的系统和方法以及用于将并行数据锁存到第二寄存器中的握手信号
公开(公告)号：US5768529A
公开(公告)日：1998-06-16
申请号：US435453
申请日：1995-05-05
IPC分类号： G06F13/42 , H04L7/04 , G06F15/163 , G06F15/17
CPC分类号： G06F13/4256
摘要： A system and method for transmitting data, using a source synchronous clocking scheme, over a communication (or data) link. A source synchronous driver (SSD) receives a micropacket of parallel data and serializes this data for transfer over the communication link. The serial data is transferred onto the communication link at a rate four times as fast as the parallel data is received by the SSD. A pair of source synchronous clocks are also transmitted across the communication link along with the serial data. The pair of clocks are the true complement of one another. A source synchronous receiver (SSR) receives the serial data and latches it into a first set of registers using the source synchronous clocks. The serial data is then latched into a second set of registers in parallel. The second set of registers are referred to as "ping-pong" registers. The ping-pong registers store the deserialized data. In parallel, a handshake signal, which is synchronized to the clock on the receiving end of the communication link indicates that there is a stream of n contiguous data words being received by the SSR. The ping pong registers guarantee that the deserialized data is available (valid) for two clock cycles. This provides a sufficient window to account for the synchronizer uncertainty on the handshake signal, while introducing minimum latency.
摘要翻译： 一种用于使用源同步计时方案通过通信（或数据）链路发送数据的系统和方法。 源同步驱动器（SSD）接收并行数据的微包并将该数据串行化以便通过通信链路传送。 将串行数据以与SSD接收的并行数据相同速度的速率传送到通信链路上。 一系列源同步时钟也与串行数据一起在通信链路上传输。 这对时钟是彼此的真正补充。 源同步接收器（SSR）使用源同步时钟接收串行数据并将其锁存到第一组寄存器中。 然后将串行数据并行锁存到第二组寄存器中。 第二组寄存器称为“乒乓”寄存器。 乒乓寄存器存储反序列化数据。 并行地，与通信链路的接收端上的时钟同步的握手信号指示存在由SSR接收的n个相邻数据字的流。 乒乓寄存器保证两个时钟周期的反序列化数据可用（有效）。 这提供了足够的窗口来解释握手信号上的同步器不确定性，同时引入最小延迟。
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3.发明授权Synchronous processor unit with interconnected, separately clocked processor sections which are automatically synchronized for data transfer operations 失效具有互连的，单独计时的处理器部分的同步处理器单元，其自动同步用于数据传输操作
公开(公告)号：US5309561A
公开(公告)日：1994-05-03
申请号：US589847
申请日：1990-09-28
CPC分类号： G06F1/06 , G06F1/12 , G06F13/423
摘要： A synchronous processor unit is divided into two sections, and each separately clocked by different clock signals. One section, containing an instruction execution unit and memory for storage of instructions and data, is clocked at a higher frequency, while the other section, containing those elements of a processor unit less frequently used, are clocked with a slower-frequencied clock. The elements of each section are intercoupled by separate and independent data buses, and selectively to one another by a buffer unit. The clock signals used by both sections are produced by a clock-generating unit which also monitors the instructions being executed by the instruction execution unit. When an instruction requiring communication between the two sections is detected, at least one predetermined transition of each of the fast and slow clocks are synchronized, and during this synchronization the separate buses of each section are coupled to one another by the buffer unit for information exchanges therebetween.
摘要翻译： 同步处理器单元分为两个部分，每个部分分别由不同的时钟信号计时。 包含用于存储指令和数据的指令执行单元和存储器的一个部分以更高的频率被计时，而包含较不频繁使用的处理器单元的那些元件的另一部分被较慢频率的时钟计时。 每个部分的元件通过单独和独立的数据总线相互耦合，并且通过缓冲单元彼此选择性地相互配合。 由两部分使用的时钟信号由时钟发生单元产生，时钟发生单元还监视由指令执行单元执行的指令。 当检测到需要两部分之间的通信的指令时，快速和慢速时钟中的每一个的至少一个预定转换被同步，并且在该同步期间，每个部分的分开的总线通过用于信息交换的缓冲器单元彼此耦合 之间。
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4.发明授权Providing shared and non-shared access to memory in a system with plural processor coherence domains 有权在具有多个处理器相干域的系统中提供对存储器的共享和非共享访问公开(公告)号：US07069306B1
公开(公告)日：2006-06-27
申请号：US09910591
申请日：2001-07-20
CPC分类号： G06F12/0817 , G06F12/0813
摘要： A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.
摘要翻译： 用于管理多处理器系统中的存储器的方法和系统包括在多处理器系统的系统相干域内定义多个处理器相干域。 处理器相干域各自包括多个处理器和处理器存储器。 每个处理器一致性域的处理器存储器中的数据的共享访问仅提供给处理器相干域内的多处理器系统的元件。 每个处理器相干域的处理器存储器中的数据的非共享访问被提供给处理器相干域内部和外部的多处理器系统的元件。
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5.发明授权Distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system 失效分发故障指示，维护和使用指示故障的数据结构，在分组交换系统中路由流量公开(公告)号：US06990063B1
公开(公告)日：2006-01-24
申请号：US09519282
申请日：2000-03-07
CPC分类号： H04Q3/68 , H04L49/1523 , H04L49/55
摘要： Methods and apparatus are disclosed for distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system. In one embodiment, a packet switching system detects faults and propagates indications of these faults to the input interfaces of a packet switch, so the packet switch can adapt the selection of a route over which to send a particular packet. Faults are identified by various components of the packet switching system and relayed to one or more switching components to generate a broadcast packet destined for all input ports (i.e., to each I/O interface in a packet switch having folded input and output interfaces). Other embodiments, generate one or more multicast or unicast packets. The I/O interface maintains one or more data structures indicating the state of various portions of the packet switching system. In one embodiment, an output availability table is maintained indicating over which path a particular destination may be reached, as well as a link availability vector indicating which output likes of the input interface may be currently used. Using these as masks against possible routes in a fully functional system, the packet switching component (e.g., I/O interface) can identify which routes are currently available for reaching the destination of the received packet. These routes can then be selected between using one of numerous deterministic and non-deterministic methods.
摘要翻译： 公开了用于分发故障指示和维护和使用指示故障的数据结构以在分组交换系统中路由业务的方法和装置。 在一个实施例中，分组交换系统检测故障并将这些故障的指示传播到分组交换机的输入接口，因此分组交换机可以适应对其发送特定分组的路由的选择。 故障由分组交换系统的各种组件识别，并被中继到一个或多个交换组件以产生目的地为所有输入端口（即，具有折叠的输入和输出接口的分组交换机中的每个I / O接口）的广播分组。 其他实施例，生成一个或多个多播或单播分组。 I / O接口保持指示分组交换系统的各个部分的状态的一个或多个数据结构。 在一个实施例中，保持输出可用性表，指示可以到达特定目的地的哪个路径，以及指示可能当前使用输入接口的哪个输出像的链路可用性向量。 使用这些作为针对全功能系统中的可能路由的掩码，分组交换组件（例如，I / O接口）可以识别当前可用于到达所接收分组的目的地的哪些路由。 然后可以使用许多确定性和非确定性方法之一来选择这些路线。
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公开(公告)号：US5686730A
公开(公告)日：1997-11-11
申请号：US747976
申请日：1996-11-12
申请人： James P. Laudon , Daniel E. Lenoski , John Manton
发明人： James P. Laudon , Daniel E. Lenoski , John Manton
摘要： A high memory capacity DIMM for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM is configured for use in a DIMM pair. In the DIMM pair, a first DIMM includes a first data memory having first and second memory bank portions for storing data, and a first state memory configured to store state information corresponding to data stored in a first memory bank. A second DIMM includes a second data memory having third and fourth memory bank portions for storing data, and a second state memory configured to store state information corresponding to data stored in a second memory bank. The first memory bank is formed from the first memory bank portion and the third memory bank portion. The second memory bank is formed from the second memory bank portion and the fourth memory bank portion.
摘要翻译： 用于基于目录的分布式共享存储器多处理器计算机系统中的高存储容量DIMM包括用于存储数据的数据存储器和用于存储对应于数据的至少一部分的状态或目录信息的状态存储器。 DIMM允许独立访问数据和状态信息。 DIMM配置为用于DIMM对。 在DIMM对中，第一DIMM包括具有用于存储数据的第一和第二存储体部分的第一数据存储器，以及配置为存储对应于存储在第一存储体中的数据的状态信息的第一状态存储器。 第二DIMM包括具有用于存储数据的第三和第四存储体部分的第二数据存储器，以及配置为存储对应于存储在第二存储体中的数据的状态信息的第二状态存储器。 第一存储体由第一存储体部分和第三存储体部分形成。 第二存储体由第二存储体部分和第四存储体部分形成。
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公开(公告)号：US4780874A
公开(公告)日：1988-10-25
申请号：US40466
申请日：1987-04-20
申请人： Daniel E. Lenoski , David J. Garcia
发明人： Daniel E. Lenoski , David J. Garcia
IPC分类号： G06F11/22 , G01R31/28 , G01R31/3185
CPC分类号： G01R31/318552
摘要： A level sensitive scan design (LSSD) diagnostic apparatus for a data processing component. Each scan unit in a shift register chain comprises a plurality of level sensitive elements, e.g., data latches, which transfer signals from their input terminals to their output terminals in response to a "Phase B" pulse train. A multiplexer is connected to each data latch for communicating run data to the input terminal of each data latch in a normal mode of operation. In test mode, the multiplexer communicates signals from the output terminal of one data latch to the input terminal of an adjacent data latch, so that the data latch signals are serially communicated through the resulting latch chain.In order to prevent the test data from propagating uncontrollably through the serially connected latches, each multiplexer includes a test latch disposed between the test data input of the multiplexer and the output terminal of the preceding data latch in the chain. The test latch is controlled by a "Phase A" pulse train signal which is interleaved with the phase B pulse train.
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8.发明授权Input-output module, processing platform and method for extending a memory interface for input-output operations 有权输入输出模块，处理平台和扩展用于输入输出操作的存储器接口的方法公开(公告)号：US07886103B2
公开(公告)日：2011-02-08
申请号：US12206501
申请日：2008-09-08
CPC分类号： G06F13/385 , G11C5/04
摘要： Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.
摘要翻译： 这里一般地描述用于扩展存储器接口的I / O模块，处理平台和方法的实施例。 在一些实施例中，I / O模块可以被配置为在诸如DIMM插槽的存储器模块插座中操作，以在主机系统中提供增加的I / O功能。 一些系统管理总线地址线和一些未使用的系统时钟信号线可以被重新配置为用于I / O模块和主机系统的PCIe交换机之间的串行数据通信的串行数据线。
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9.发明授权Method and apparatus for distributing packets across multiple paths leading to a destination 有权用于在通往目的地的多个路径上分发分组的方法和装置公开(公告)号：US06826186B1
公开(公告)日：2004-11-30
申请号：US09519715
申请日：2000-03-07
IPC分类号： H04L1228
摘要： According to the invention, methods and apparatus are disclosed for selecting one of multiple of paths between two points over which to route a data item based on the destination of the data item and the traffic between the two points over the multiple paths. A switching system can use the disclosed methods and apparatus to more efficiently distribute data packets among switching fabrics than currently accomplished by known techniques. In one implementation, distribution cycles have been established for sending data between two points, where each path between the endpoints is used a predetermined number of times (e.g., one, two) within each cycle. To economize the amount of traffic data collected, the multiple paths can be partitioned into subsets for which traffic data is maintained only for the current subset. Additionally, the distribution of traffic between the two points can be further partitioned into traffic of a particular type or priority between the two points.
摘要翻译： 根据本发明，公开了用于选择基于数据项的目的地路由数据项的两个点之间的多个路径中的一个路径和多个路径上的两个点之间的业务的方法和装置。 交换系统可以使用所公开的方法和装置来更有效地分配交换结构中的数据分组，而不是目前通过已知技术实现的数据分组。 在一个实现中，已经建立了分发周期，用于在两个点之间发送数据，其中端点之间的每个路径在每个周期内被使用预定次数（例如，一个，两个）。 为了节约收集的流量数据量，可以将多个路径划分为仅为当前子集维护流量数据的子集。 此外，两点之间的业务分配可以进一步划分为两点之间的特定类型或优先级的业务。
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10.发明授权System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer 失效在多处理器计算机中维护虚拟到物理内存转换的一致性的系统和方法公开(公告)号：US06182195B2
公开(公告)日：2001-01-30
申请号：US09123473
申请日：1998-07-28
申请人： James P. Laudon , Daniel E. Lenoski
发明人： James P. Laudon , Daniel E. Lenoski
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/1027 , G06F12/1072 , G06F2212/682
摘要： A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.
摘要翻译： 一种用于在系统中的多个请求者的虚拟到物理存储器转换之间维持一致性的多处理器计算机系统和方法。 毒物位与系统中的内存块相关联。 毒素位被设置为指示内存块的虚拟到物理内存转换过时。 如果设置了毒性比特，则响应于一个请求者对存储器块的访问而产生异常，从而向请求者指示存储器块的虚拟到物理存储器转换条目是否陈旧。 然后，利用对应于存储器块的新物理位置的虚拟存储器转换来更新存储器块的虚拟到物理存储器转换。 在具有基于高速缓存的多处理器系统的实施例中，该方法还包括使存储器块的所有高速缓存副本无效的步骤。 在这种情况下，无效步骤和设置步骤必须作为原子操作执行。
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