-
公开(公告)号：US06943606B2
公开(公告)日：2005-09-13
申请号：US09891466
申请日：2001-06-27
申请人： Davied S. Dunning , Chamath Abhayagunawardhana , Ken Drottar , Richard S. Jensen , Robert Glenn
发明人： Davied S. Dunning , Chamath Abhayagunawardhana , Ken Drottar , Richard S. Jensen , Robert Glenn
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00286
摘要： A phase interpolator interpolates between a plurality of clock phases using a plurality of switching legs coupled to a common output. Each switching leg includes a pair of differential switching transistors each having a gate and two additional terminals, one of which is coupled to said common output. The gates are coupled to respective ones of the plurality of clock phases and their complements. Tails couple the other terminals of said switching transistors to ground. Each tail made up of a plurality of transistors. A load coupling the common output to a voltage.
摘要翻译： 相位插值器使用耦合到公共输出的多个开关支路在多个时钟相位之间内插。 每个开关支路包括一对差分开关晶体管，每个具有栅极和两个附加端子，其中一个连接到所述公共输出端。 门耦合到多个时钟相位中的相应时钟相位及其补码。 尾部将所述开关晶体管的其它端子耦合到地。 每个尾部由多个晶体管组成。 将公共输出耦合到电压的负载。
-
2.发明授权Method and apparatus for a tracking data receiver compensating for deterministic jitter 有权跟踪数据接收机补偿确定性抖动的方法和装置公开(公告)号：US06765975B2
公开(公告)日：2004-07-20
申请号：US09741319
申请日：2000-12-19
IPC分类号： H04L2536
CPC分类号： H04L7/0338 , H04L7/033
摘要： A tracking data receiver which can compensate for deterministic jitter is disclosed. The device utilizes a history of past data received to determine which of multiple samples taken within a bit period to utilize. Due to deterministic jitter that can occur in data signal communication, the delay of waveform development varies with the ratio of 0's to 1's transmitted prior to the bit period being observed. The present invention exploits the predictable nature of the deterministic jitter to decide which sample to choose.
摘要翻译： 公开了可补偿确定性抖动的跟踪数据接收机。 该设备利用接收到的过去数据的历史来确定在一个位周期内采用的多个样本中的哪个采样。 由于可能发生在数据信号通信中的确定性抖动，波形发展的延迟随着观察到比特周期之前发送的0到1的比率而变化。 本发明利用确定性抖动的可预测性来决定要选择哪个样本。
-
公开(公告)号：US07474714B2
公开(公告)日：2009-01-06
申请号：US10334935
申请日：2002-12-31
IPC分类号： H04L27/00
CPC分类号： H04L7/033
摘要： A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.
摘要翻译： 数字电子系统内的接收装置包括采样单元，选举块和本地时钟相位调整单元。 采样单元在三个时间点以一个位周期的一半的间隔对输入行进行采样。 采样单元将采样过程中获得的值传递给选举块。 选民块决定是否向本地时钟相位调整单位输出向上或向下的投票。 选举块通过上下控制信号与本地时钟相位调整单元进行通信。 本地时钟相位调整单元确定是否应调整本地时钟相位，如果是，是否提前或延迟本地时钟相位。 如果选民块观察到某些元稳定条件，则选民块将以一个方向投票，以将该制度推出元稳定状态。
-
公开(公告)号：US07126986B2
公开(公告)日：2006-10-24
申请号：US10262359
申请日：2002-09-30
CPC分类号： G06F1/12 , H03L7/0814 , H03L7/089 , H03L7/093 , H04L7/0008 , H04L7/0025
摘要： A method and system for improved phase tracking in communication systems is disclosed. In one embodiment, a method, comprises identifying a slow-time varying phase drift on a link by counting long term beats; calibrating an interpolator with the phase drift; predicting a future phase drift; and updating the interpolator periodically with the future phase drift prediction.
摘要翻译： 公开了一种用于改进通信系统中的相位跟踪的方法和系统。 在一个实施例中，一种方法包括通过计数长期节拍来识别链路上的慢时变化相位漂移; 校准具有相位漂移的内插器; 预测未来相位漂移; 以及随着未来的相位漂移预测周期性地更新内插器。
-
公开(公告)号：US06446235B1
公开(公告)日：2002-09-03
申请号：US09386474
申请日：1999-08-31
IPC分类号： G06F1110
CPC分类号： H04L1/0061 , H03M13/09 , H04L1/0041
摘要： An error detection technique uses a cumulative error detecting code (such as a cumulative CRC checksum or the like). At the source node (transmitter side) an error detecting code of a previous cell is stored. The next cell to be transmitted is received and the error detecting code of the previous cell is appended to the next cell. A next error detecting code is calculated as a function of at least a portion of the next cell to be transmitted and the previous error detecting code appended thereto. The previous error detecting code appended to the next cell is replaced with the next error detecting code, and the next cell including the next error detecting code appended thereto is transmitted. In this manner, the cumulative error detecting code is calculated over the current cell and a previous error detecting code. Thus, the cumulative error detecting code can be used to detect bit errors in each individual cell as well as to detect one or more missing or dropped cells.
摘要翻译： 错误检测技术使用累积检错码（如累积CRC校验和等）。 在源节点（发射机侧），存储先前小区的错误检测码。 接收到要发送的下一个小区，并将上一个小区的错误检测码追加到下一个小区。 根据要发送的下一个小区的至少一部分和附加的先前的错误检测码，计算下一个错误检测码。 附加到下一个单元的先前错误检测码被下一个错误检测码替换，并且发送包括附加在其上的下一个检错码的下一个单元。 以这种方式，在当前小区和先前的错误检测码上计算累积检错码。 因此，可以使用累积检错码来检测每个单独的单元中的位错误，以及检测一个或多个丢失或丢弃的单元。
-
公开(公告)号：US07436215B2
公开(公告)日：2008-10-14
申请号：US10676712
申请日：2003-09-30
申请人： Ken Drottar , Zale T Schoenborn
发明人： Ken Drottar , Zale T Schoenborn
IPC分类号： H03K19/094 , H03K19/0175 , H03K19/20
CPC分类号： H03F3/3055 , H03F3/24 , H03F3/60 , H03F2200/423 , H04B2001/0408
摘要： In some embodiments, a transmitter includes a first circuit coupled to an input port of the transmitter, and a second circuit coupled to the first circuit and to an output port of the transmitter, wherein the first circuit is sized with respect to the second circuit such that for a pulse signal applied to the input port, the transmitter generates an output signal having a rise-time and a fall-time that are substantially equal at the output port.
摘要翻译： 在一些实施例中，发射机包括耦合到发射机的输入端口的第一电路和耦合到第一电路和发射机的输出端口的第二电路，其中第一电路的尺寸相对于第二电路的尺寸如 对于施加到输入端口的脉冲信号，发射器产生具有在输出端口处基本相等的上升时间和下降时间的输出信号。
-
公开(公告)号：US20080231331A1
公开(公告)日：2008-09-25
申请号：US11726911
申请日：2007-03-22
申请人： Vishnu Balraj , Terry Baucom , Amir Bashir , Huimin Chen , Ken Drottar , Naveed Khan , Duane Quiet , Andrew M. Volk
发明人： Vishnu Balraj , Terry Baucom , Amir Bashir , Huimin Chen , Ken Drottar , Naveed Khan , Duane Quiet , Andrew M. Volk
IPC分类号： H03L7/00
摘要： Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.
摘要翻译： 公开了用于产生扩频时钟的方法和电路的实施例。
-
公开(公告)号：US07227414B2
公开(公告)日：2007-06-05
申请号：US10607799
申请日：2003-06-27
申请人： Ken Drottar
发明人： Ken Drottar
IPC分类号： H03F3/16
CPC分类号： H03F1/42 , H03F1/086 , H03F1/34 , H03F1/342 , H03F3/16 , H03F3/45237 , H03F2200/36 , H03K19/018528
摘要： In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，一种装置包括放大器，具有耦合到放大器的输出的输入的第一反相器和具有耦合到第一反相器的输出的输入的第二反相器和输出，其中第二反相器的输出 反馈到放大器的输入。 描述和要求保护其他实施例。
-
9.发明授权公开(公告)号：US07203853B2
公开(公告)日：2007-04-10
申请号：US10302295
申请日：2002-11-22
申请人： Andrew W. Martwick , Ken Drottar , David S. Dunning , Zale T. Schoenborn , Andrew M. Volk , Ronald W. Swartz , Dennis J. Miller
发明人： Andrew W. Martwick , Ken Drottar , David S. Dunning , Zale T. Schoenborn , Andrew M. Volk , Ronald W. Swartz , Dennis J. Miller
IPC分类号： G06F12/00
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3253 , Y02D10/151
摘要： An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.
摘要翻译： 描述了串行数据链路上的低延迟功率管理的装置和方法。 在一个实施例中，该方法包括在电气空闲状态期间在接收机操作期间检测电空闲出口状况。 一旦检测到，则根据一个或多个接收到的数据同步训练模式执行数据同步。 最后，当在确定的同步重建周期内执行同步时，接收机将根据正常功率状态恢复操作。 因此，所描述的实施例示出了3GIO链路内的电源管理的开环低延迟功率恢复操作。
-
公开(公告)号：US06687840B1
公开(公告)日：2004-02-03
申请号：US09557099
申请日：2000-04-21
申请人： Ken Drottar , David S. Dunning
发明人： Ken Drottar , David S. Dunning
IPC分类号： G06F1342
CPC分类号： H04L47/10 , H04L69/14 , H04L69/324 , Y02D50/30
摘要： A method, apparatus, and system are provided for multi-link extensions and bundle skew management. According to one embodiment, multiple parallel links between two or more devices are combined into a single channel, and cells on the various links are received in a round-robin order, and variations in flight time between the various links are compensated through a timer at each receive port of the bundle.
摘要翻译： 提供了一种方法，装置和系统用于多链路扩展和捆绑偏移管理。 根据一个实施例，两个或多个设备之间的多个并行链路被组合成单个信道，并且以循环次序接收各个链路上的小区，并且通过定时器在各个链路之间的飞行时间的变化被补偿 每个接收端口的捆绑。
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.023 秒)
