公开(公告)号：US5831301A

公开(公告)日：1998-11-03

申请号：US14523

申请日：1998-01-28

申请人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

发明人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。

公开(公告)号：US6063658A

公开(公告)日：2000-05-16

申请号：US172865

申请日：1998-10-15

申请人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

发明人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。

公开(公告)号：US07651902B2

公开(公告)日：2010-01-26

申请号：US11737989

申请日：2007-04-20

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L21/338 ,  H01L23/62

CPC分类号： H01L21/76243 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

摘要翻译： 以不同晶体取向的半导体岛为特征的混合基板和形成这种混合基板的方法。 该方法涉及使用SIMOX工艺来形成绝缘层。 绝缘层可以将不同晶体取向中的至少一个的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。

公开(公告)号：US07750406B2

公开(公告)日：2010-07-06

申请号：US11877871

申请日：2007-10-24

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L23/62 ,  H01L29/94

CPC分类号： H01L21/76264

摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

摘要翻译： 设计结构体现在机器可读介质中，用于设计，制造或测试设计，其中设计结构包括以混合衬底形成的器件，其特征在于具有不同晶体取向的半导体岛。 绝缘层将至少一个不同晶体取向的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。

公开(公告)号：US20080258181A1

公开(公告)日：2008-10-23

申请号：US11737989

申请日：2007-04-20

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/76243 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

摘要翻译： 以不同晶体取向的半导体岛为特征的混合基板和形成这种混合基板的方法。 该方法涉及使用SIMOX工艺来形成绝缘层。 绝缘层可以将不同晶体取向中的至少一个的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。

公开(公告)号：US20080258222A1

公开(公告)日：2008-10-23

申请号：US11877871

申请日：2007-10-24

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L27/12

CPC分类号： H01L21/76264

摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

摘要翻译： 设计结构体现在机器可读介质中，用于设计，制造或测试设计，其中设计结构包括以混合衬底形成的器件，其特征在于具有不同晶体取向的半导体岛。 绝缘层将至少一个不同晶体取向的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。

公开(公告)号：US07737504B2

公开(公告)日：2010-06-15

申请号：US11759981

申请日：2007-06-08

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L29/772

CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

公开(公告)号：US07268028B1

公开(公告)日：2007-09-11

申请号：US11279962

申请日：2006-04-17

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L21/8244 ,  H01L21/8242

CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

公开(公告)号：US20080242016A1

公开(公告)日：2008-10-02

申请号：US12117232

申请日：2008-05-08

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L21/8238

CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。

公开(公告)号：US20080203492A1

公开(公告)日：2008-08-28

申请号：US12117371

申请日：2008-05-08

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L27/092

CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.