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    Integrated decision feedback equalizer and clock and data recovery
    2.
    发明申请
    Integrated decision feedback equalizer and clock and data recovery 失效
    集成决策反馈均衡器和时钟和数据恢复

    公开(公告)号：US20050135471A1

    公开(公告)日：2005-06-23

    申请号：US10823252

    申请日：2004-04-13

    Applicant: Davide Tonietto ,  Afshin Momtaz

    Inventor： Davide Tonietto ,  Afshin Momtaz

    IPC: H03L7/08 ,  H03L7/089 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H03K5/159

    CPC classification number: H04L25/03057 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349

    Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

    Abstract translation: 在集成判决反馈均衡器和时钟和数据恢复电路中，可以共享一个或多个触发器和/或锁存器。 一个或多个触发器和/或锁存器可用于判决反馈均衡器中的重新定时操作以及时钟恢复电路中的相位检测操作。 可以使用触发器和/或锁存器的输出来产生用于判决反馈均衡器的反馈信号。 触发器和/或锁存器的输出可用于产生驱动时钟恢复电路中的电荷泵的信号。

    Integrated decision feedback equalizer and clock and data recovery
    3.
    发明授权
    Integrated decision feedback equalizer and clock and data recovery 失效
    集成决策反馈均衡器和时钟和数据恢复

    公开(公告)号：US07822113B2

    公开(公告)日：2010-10-26

    申请号：US10823252

    申请日：2004-04-13

    Applicant: Davide Tonietto ,  Afshin Momtaz

    Inventor： Davide Tonietto ,  Afshin Momtaz

    IPC: H03H7/30

    CPC classification number: H04L25/03057 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349

    Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

    Abstract translation: 在集成判决反馈均衡器和时钟和数据恢复电路中，可以共享一个或多个触发器和/或锁存器。 一个或多个触发器和/或锁存器可用于判决反馈均衡器中的重新定时操作和时钟恢复电路中的相位检测操作。 可以使用触发器和/或锁存器的输出来产生用于判决反馈均衡器的反馈信号。 触发器和/或锁存器的输出可用于产生驱动时钟恢复电路中的电荷泵的信号。

    Low Latency High Bandwidth CDR Architecture
    7.
    发明申请
    Low Latency High Bandwidth CDR Architecture 有权
    低延迟高带宽CDR体系结构

    公开(公告)号：US20120328063A1

    公开(公告)日：2012-12-27

    申请号：US13168861

    申请日：2011-06-24

    Applicant: Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

    Inventor： Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

    IPC: H04L7/02

    CPC classification number: H04L7/0079 ,  H03L7/0812 ,  H04L7/033

    Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

    Abstract translation: 提供了低延迟高带宽时钟和数据恢复（CDR）系统。 例如，存在低延迟高带宽CDR系统，其包括解复用器，其被配置为根据第一等待时间将高频输入数据流转换为低频输出数据流，并且相位误差处理器至少部分地被嵌入到解复用器中并且被配置为确定 根据第二等待时间，高频输入数据流的数据流相位误差。 嵌入式相位误差处理器允许由于解复用器和相位误差处理器而导致的CDR系统的总等待时间的一部分小于第一和第二延迟的和。

    Distributed threshold adjustment for high speed receivers
    8.
    发明授权
    Distributed threshold adjustment for high speed receivers 有权
    高速接收机的分布式阈值调整

    公开(公告)号：US08077060B2

    公开(公告)日：2011-12-13

    申请号：US12582442

    申请日：2009-10-20

    Applicant: Afshin Momtaz ,  Namik K. Kocaman ,  Bharath Raghavan

    Inventor： Afshin Momtaz ,  Namik K. Kocaman ,  Bharath Raghavan

    IPC: H03M7/00

    CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2203/45686

    Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

    Abstract translation: 根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。 在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。 在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。 在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

    Threshold adjust system and method
    9.
    发明授权
    Threshold adjust system and method 失效
    阈值调整系统和方法

    公开(公告)号：US07769110B2

    公开(公告)日：2010-08-03

    申请号：US11128905

    申请日：2005-05-13

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H04L25/06

    CPC classification number: H04L25/061 ,  H04L7/033 ,  H04L25/03057

    Abstract: An adaptive algorithm is implemented that optimizes the slicer threshold by optimizing the tail distribution of a “+1” and “−1” histogram. Through the use of a low resolution and under-sampled ADC, a histogram of received bit may be created. The difference between the y-intersects of lines derived from the “+1” and “−1” histogram is used to determine an error function. The algorithm iteratively updates the threshold value based on this error function.

    Abstract translation: 实现了通过优化“+1”和“-1”直方图的尾部分布来优化限幅器阈值的自适应算法。 通过使用低分辨率和欠采样ADC，可以创建接收位的直方图。 使用从“+1”和“-1”直方图导出的线的y相交之间的差异来确定误差函数。 该算法基于该误差函数迭代地更新阈值。

    Decision feedback equalizer and clock and data recovery circuit for high speed applications
    10.
    发明授权
    Decision feedback equalizer and clock and data recovery circuit for high speed applications 有权
    决策反馈均衡器和时钟和数据恢复电路，适用于高速应用

    公开(公告)号：US07436882B2

    公开(公告)日：2008-10-14

    申请号：US10774965

    申请日：2004-02-09

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H03H7/30 ,  H03K5/159 ,  H03D3/24

    CPC classification number: H04L25/03057 ,  H04B10/2507 ,  H04L7/0004 ,  H04L7/033 ,  H04L2025/0349

    Abstract: A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or phase fixed relative to the equalized data is extracted from the equalized data. The extracted clock is used to clock a retimer to generate recovered data.

    Abstract translation: 用于传送数据的方法包括均衡接收的数据以减少接收到的数据中的信道相关失真。 从均衡数据中提取相对于均衡数据具有频率和/或相位固定的时钟。 提取的时钟用于对重定时器进行计时以产生恢复的数据。

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