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    Integrated decision feedback equalizer and clock and data recovery
    2.
    发明申请
    Integrated decision feedback equalizer and clock and data recovery 失效
    集成决策反馈均衡器和时钟和数据恢复

    公开(公告)号：US20050135471A1

    公开(公告)日：2005-06-23

    申请号：US10823252

    申请日：2004-04-13

    Applicant: Davide Tonietto ,  Afshin Momtaz

    Inventor： Davide Tonietto ,  Afshin Momtaz

    IPC: H03L7/08 ,  H03L7/089 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H03K5/159

    CPC classification number: H04L25/03057 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349

    Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

    Abstract translation: 在集成判决反馈均衡器和时钟和数据恢复电路中，可以共享一个或多个触发器和/或锁存器。 一个或多个触发器和/或锁存器可用于判决反馈均衡器中的重新定时操作以及时钟恢复电路中的相位检测操作。 可以使用触发器和/或锁存器的输出来产生用于判决反馈均衡器的反馈信号。 触发器和/或锁存器的输出可用于产生驱动时钟恢复电路中的电荷泵的信号。

    Integrated decision feedback equalizer and clock and data recovery
    3.
    发明授权
    Integrated decision feedback equalizer and clock and data recovery 失效
    集成决策反馈均衡器和时钟和数据恢复

    公开(公告)号：US07822113B2

    公开(公告)日：2010-10-26

    申请号：US10823252

    申请日：2004-04-13

    Applicant: Davide Tonietto ,  Afshin Momtaz

    Inventor： Davide Tonietto ,  Afshin Momtaz

    IPC: H03H7/30

    CPC classification number: H04L25/03057 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349

    Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

    Abstract translation: 在集成判决反馈均衡器和时钟和数据恢复电路中，可以共享一个或多个触发器和/或锁存器。 一个或多个触发器和/或锁存器可用于判决反馈均衡器中的重新定时操作和时钟恢复电路中的相位检测操作。 可以使用触发器和/或锁存器的输出来产生用于判决反馈均衡器的反馈信号。 触发器和/或锁存器的输出可用于产生驱动时钟恢复电路中的电荷泵的信号。

    INDUCTORS FOR CHIP TO CHIP NEAR FIELD COMMUNICATION
    7.
    发明申请
    INDUCTORS FOR CHIP TO CHIP NEAR FIELD COMMUNICATION 审中-公开

    公开(公告)号：US20180366535A1

    公开(公告)日：2018-12-20

    申请号：US15625731

    申请日：2017-06-16

    Applicant: Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

    Inventor： Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

    IPC: H01L49/02 ,  H01L23/00 ,  H04B5/00

    Abstract: A device includes a first inductor positioned on a first substrate. The first inductor has at least one turn in a plane that is perpendicular to a plane of the first substrate. The first inductor is positioned for near field coupling with a second inductor. The second inductor is positioned on a second substrate, with at least one turn that is in a plane perpendicular to a plane of the second substrate. The second inductor is substantially parallel to the first inductor. Such an arrangement may be used for near field coupling, including edge-to-edge coupling, between two integrated circuits.

    System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system
    8.
    发明授权
    System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system 有权
    在10千兆以太网/光纤通道系统中可编程调节增益和频率响应的系统和方法

    公开(公告)号：US08090047B2

    公开(公告)日：2012-01-03

    申请号：US12795808

    申请日：2010-06-08

    Applicant: Ichiro Fujimori ,  Davide Tonietto

    Inventor： Ichiro Fujimori ,  Davide Tonietto

    IPC: H04L27/00

    CPC classification number: H04B10/291

    Abstract: Systems and methods for optimizing operation of a transceiver device are disclosed. The method may include parallel processing an input signal through a first path having a first frequency response and a second path having a second frequency response. The second frequency response may be higher than the first frequency response. Signals from the first and second paths may be combined, creating an output signal having a desired gain and frequency. The parallel processing may adjust a gain of at least one of the first path and the second path. The parallel processing may equalize at least one of the first frequency response and the second frequency response. The input signal may be from a 10 GBit Ethernet channel and/or a Fibre channel.

    Abstract translation: 公开了一种用于优化收发器设备的操作的系统和方法。 该方法可以包括通过具有第一频率响应的第一路径和具有第二频率响应的第二路径并行处理输入信号。 第二频率响应可能高于第一频率响应。 可以组合来自第一和第二路径的信号，产生具有所需增益和频率的输出信号。 并行处理可以调整第一路径和第二路径中的至少一个的增益。 并行处理可以均衡第一频率响应和第二频率响应中的至少一个。 输入信号可以来自10GBit以太网信道和/或光纤信道。

    Bit stream conditioning circuit having adjustable input sensitivity
    9.
    发明授权
    Bit stream conditioning circuit having adjustable input sensitivity 失效
    位流调节电路具有可调输入灵敏度

    公开(公告)号：US08014471B2

    公开(公告)日：2011-09-06

    申请号：US11970191

    申请日：2008-01-07

    Applicant: Davide Tonietto ,  Ali Ghiasi

    Inventor： Davide Tonietto ,  Ali Ghiasi

    IPC: H04L27/06

    CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

    Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 限幅放大器根据输入信号的相应动态范围，将相应的增益应用于RX路径和TX路径。

    Bit stream conditioning circuit having adjustable PLL bandwidth
    10.
    发明授权
    Bit stream conditioning circuit having adjustable PLL bandwidth 有权
    位流调节电路具有可调节的P​​LL带宽

    公开(公告)号：US07321612B2

    公开(公告)日：2008-01-22

    申请号：US10418035

    申请日：2003-04-17

    Applicant: Davide Tonietto ,  Ali Ghiasi

    Inventor： Davide Tonietto ,  Ali Ghiasi

    IPC: H04B1/38

    CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

    Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 时钟和数据恢复电路具有可调节的锁相环（PLL）带宽，其被设置为对应于服务的高速比特流的抖动带宽。

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