公开(公告)号：US06807225B1

公开(公告)日：2004-10-19

申请号：US09584598

申请日：2000-05-31

Applicant: Davide Tonietto ,  Andre M. Bischof

Inventor： Davide Tonietto ,  Andre M. Bischof

IPC: H04B138

CPC classification number: H03L7/087 ,  H03L7/10 ,  H03L2207/06 ,  H04L7/0004 ,  H04L7/033

Abstract: A circuit and method is disclosed for self trimming in frequency acquisition and clock recovery. The circuit can be simplified as having a VCO in communication with three loops including a trimming loop, a frequency loop and a phase loop. The trimming loop includes a ramp generator for supplying a steady increase of bias current to the VCO causing the frequency of the VCO to increase. At each step, the averaged output of the frequency detector is measured by a comparator. A decision circuit included in the trimming loop registers the output of the comparator in digital format. The trimming loop continues until the decision circuit detects a long string of positives followed by a long string of negatives and at this point, the trimming loop is shut off and the frequency loop is in operation. The frequency loop drives the VCO frequency to within a small difference of the incoming data frequency. The phase loop cleans up the data and locks the phase.

Abstract translation: 公开了用于频率采集和时钟恢复中的自整定的电路和方法。 该电路可以简化为具有与三个环路通信的VCO，包括修整环路，频率环路和相位环路。 修整回路包括斜坡发生器，用于向VCO提供稳定增加的偏置电流，从而使VCO的频率增加。 在每个步骤中，频率检测器的平均输出由比较器测量。 包括在微调循环中的判定电路以数字格式注册比较器的输出。 修整循环继续，直到判定电路检测到长串正序，然后是长串负片，此时，修整环路被关闭，并且频率环路正在运行。 频率环路将VCO频率驱动到输入数据频率的小差异之内。 相位循环清理数据并锁定相位。

公开(公告)号：US20180366535A1

公开(公告)日：2018-12-20

申请号：US15625731

申请日：2017-06-16

Applicant: Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

Inventor： Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

IPC: H01L49/02 ,  H01L23/00 ,  H04B5/00

Abstract: A device includes a first inductor positioned on a first substrate. The first inductor has at least one turn in a plane that is perpendicular to a plane of the first substrate. The first inductor is positioned for near field coupling with a second inductor. The second inductor is positioned on a second substrate, with at least one turn that is in a plane perpendicular to a plane of the second substrate. The second inductor is substantially parallel to the first inductor. Such an arrangement may be used for near field coupling, including edge-to-edge coupling, between two integrated circuits.

公开(公告)号：US08090047B2

公开(公告)日：2012-01-03

申请号：US12795808

申请日：2010-06-08

Applicant: Ichiro Fujimori ,  Davide Tonietto

Inventor： Ichiro Fujimori ,  Davide Tonietto

IPC: H04L27/00

CPC classification number: H04B10/291

Abstract: Systems and methods for optimizing operation of a transceiver device are disclosed. The method may include parallel processing an input signal through a first path having a first frequency response and a second path having a second frequency response. The second frequency response may be higher than the first frequency response. Signals from the first and second paths may be combined, creating an output signal having a desired gain and frequency. The parallel processing may adjust a gain of at least one of the first path and the second path. The parallel processing may equalize at least one of the first frequency response and the second frequency response. The input signal may be from a 10 GBit Ethernet channel and/or a Fibre channel.

Abstract translation: 公开了一种用于优化收发器设备的操作的系统和方法。 该方法可以包括通过具有第一频率响应的第一路径和具有第二频率响应的第二路径并行处理输入信号。 第二频率响应可能高于第一频率响应。 可以组合来自第一和第二路径的信号，产生具有所需增益和频率的输出信号。 并行处理可以调整第一路径和第二路径中的至少一个的增益。 并行处理可以均衡第一频率响应和第二频率响应中的至少一个。 输入信号可以来自10GBit以太网信道和/或光纤信道。

公开(公告)号：US08014471B2

公开(公告)日：2011-09-06

申请号：US11970191

申请日：2008-01-07

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04L27/06

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 限幅放大器根据输入信号的相应动态范围，将相应的增益应用于RX路径和TX路径。

公开(公告)号：US07321612B2

公开(公告)日：2008-01-22

申请号：US10418035

申请日：2003-04-17

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04B1/38

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 时钟和数据恢复电路具有可调节的锁相环（PLL）带宽，其被设置为对应于服务的高速比特流的抖动带宽。

公开(公告)号：US07206366B2

公开(公告)日：2007-04-17

申请号：US10337567

申请日：2003-01-07

Applicant: Ichiro Fujimori ,  Davide Tonietto

Inventor： Ichiro Fujimori ,  Davide Tonietto

IPC: H04B1/10 ,  H03H7/30 ,  H03D1/00 ,  G11B5/02

CPC classification number: H04B10/291

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster coupled to the signal divider may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device. An equalizer coupled to the signal divider may be configured to equalize the equalization adjustment signal within the multimode PHY device. A summer coupled to the equalizer and signal adjuster may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device to create an output equalized signal having a desired gain and/or frequency response.

Abstract translation: 本发明的各方面可以提供用于调整多模PHY设备的输入信号的增益和/或频率响应的方法和系统。 信号分配器可以在接收到输入信号时将输入信号分配成增益调整信号和/或均衡调整信号。 耦合到信号分配器的信号调节器可以调整多模PHY器件内的分配增益调整信号的增益。 耦合到信号分配器的均衡器可以被配置为均衡多模PHY设备内的均衡调整信号。 耦合到均衡器和信号调节器的加法器可以适于将经调整的调整信号和多模PHY装置内的均衡均衡调整信号相加以产生具有期望增益和/或频率响应的输出均衡信号。

公开(公告)号：US09553600B1

公开(公告)日：2017-01-24

申请号：US15187161

申请日：2016-06-20

Applicant: Marc-Andre Lacroix ,  Henry Wong ,  Davide Tonietto

Inventor： Marc-Andre Lacroix ,  Henry Wong ,  Davide Tonietto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/00 ,  H04L7/00

CPC classification number: H03M1/0624 ,  G06F1/10 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225 ,  H04L7/0008

Abstract: The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.

Abstract translation: 本公开提供了一种用于校正时间交织的模数转换器中的时钟偏移的系统，电路和方法。 沿相应的通道接收至少两个时钟信号。 通过对通道应用一个或多个第一调整因子直到第一时钟信号的边沿与参考信号的转换点对准来考虑承载第一时钟信号的第一通道的延迟。 第一个时钟信号被交换到第二个信道，反之亦然。 将由第一时钟信号采样的参考信号的值与由第二时钟信号采样的参考信号的值进行比较，以确定第二信道相对于第一信道的偏斜，以及一个或多个第二信道 基于确定的第二通道的倾斜度，将调整因子应用于第二通道。

公开(公告)号：US08265132B2

公开(公告)日：2012-09-11

申请号：US12419100

申请日：2009-04-06

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H03K5/159

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, such as copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速位流接口模块包括线路侧接口，电路板侧接口和信号调理电路。 线路侧接口包括接收线路侧介质的介质耦合器，例如铜介质或光学介质。 板侧接口将高速串行比特流接口模块耦合到PCB。 信号调理电路通信耦合到线路侧接口和电路板侧接口。 信号调理电路从线路侧接口接收RX信号，对RX信号进行调节，并将接收信号提供给电路板侧接口。 信号调理电路从电路板侧接口接收TX信号，调节TX信号，并向板侧接口提供TX信号。

公开(公告)号：US07974337B2

公开(公告)日：2011-07-05

申请号：US12606751

申请日：2009-10-27

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Kyong-Sik Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Kyong-Sik Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03H7/30

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract translation: 公开了各种示例性实施例。 根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。 适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

公开(公告)号：US07733998B2

公开(公告)日：2010-06-08

申请号：US11695405

申请日：2007-04-02

Applicant: Ichiro Fujimori ,  Davide Tonietto

Inventor： Ichiro Fujimori ,  Davide Tonietto

IPC: H04B1/10

CPC classification number: H04B10/291

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.

Abstract translation: 本发明的各方面可以提供用于调整多模PHY设备的输入信号的增益和/或频率响应的方法和系统。 信号分配器（704）可以在接收到输入信号时将输入信号分配成增益调整信号和/或均衡调整信号。 耦合到信号分配器（704）的信号调节器（702）可以调整多模PHY设备（130）内的分配增益调整信号的增益。 耦合到信号分配器（704）的均衡器（706）可以被配置为均衡多模PHY设备（130）内的均衡调整信号。 耦合到均衡器（706）和信号调节器（702）的加法器（708）可以适于将经调整的调整信号和多模PHY装置（130）内的均衡均衡调整信号相加，以产生输出均衡信号（712） 具有期望的增益和/或频率响应。