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    Configurable high-speed memory interface subsystem
    1.
    发明申请
    Configurable high-speed memory interface subsystem 有权
    可配置的高速内存接口子系统

    公开(公告)号：US20070033337A1

    公开(公告)日：2007-02-08

    申请号：US11198416

    申请日：2005-08-05

    申请人： Derrick Butt ,  Cheng-Gang Kong ,  Terence Magee

    发明人： Derrick Butt ,  Cheng-Gang Kong ,  Terence Magee

    IPC分类号： G06F13/00

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4096 ,  G11C2207/2254

    摘要： A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.

    摘要翻译： 核心包括写逻辑IP块，读逻辑IP块，主延迟IP块以及地址和控制IP块。 写入逻辑IP块可以被配置为将数据从存储器控制器传送到双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）。 读逻辑IP块可以被配置为将来自双数据速率（DDR）同步动态随机存取存储器（SDRAM）的数据传送到存储器控制器。 主延迟IP块可以被配置为为读逻辑IP块生成一个或多个延迟。 地址和控制逻辑IP块可以被配置为控制写逻辑IP块和读逻辑IP块。 核心通常配置为耦合双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）和存储器控制器。

    Feedback programmable data strobe enable architecture for DDR memory applications
    2.
    发明申请
    Feedback programmable data strobe enable architecture for DDR memory applications 有权
    用于DDR存储器应用的反馈可编程数据选通使能架构

    公开(公告)号：US20060288175A1

    公开(公告)日：2006-12-21

    申请号：US11154401

    申请日：2005-06-16

    申请人： Hui-Yin Seto ,  Derrick Butt ,  Cheng-Gang Kong

    发明人： Hui-Yin Seto ,  Derrick Butt ,  Cheng-Gang Kong

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4239

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为通过多个输入/输出线读取和写入数据。 第二电路可以包括多个部分。 每个部分可以被配置为向负载输出线呈现控制信号，并通过负载输入线接收控制信号的反馈。 每个部分的负载输入线和负载输出线可以连接到被配置为匹配连接到多个输入/输出线中的每一个的相应存储器负载的负载电路。

    Method and/or apparatus for training DQS strobe gating
    3.
    发明申请
    Method and/or apparatus for training DQS strobe gating 失效
    用于训练DQS选通门控的方法和/或装置

    公开(公告)号：US20070002642A1

    公开(公告)日：2007-01-04

    申请号：US11173529

    申请日：2005-07-01

    申请人： Derrick Butt ,  Hui-Yin Seto

    发明人： Derrick Butt ,  Hui-Yin Seto

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G06F13/4059 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2254

    摘要： A method for calibrating read data strobe gating including the steps of: (A) performing a coarse timing adjustment configured to determine a coarse delay setting that produces invalid data, (B) performing a medium timing adjustment configured to adjust a medium delay setting and the coarse delay setting until valid data is detected, (C) performing a fine timing adjustment configured to adjust the medium delay setting and a fine delay setting until valid data is detected and (D) adding one-half cycle to a gating delay determined by the coarse, the medium and the fine delay settings.

    摘要翻译： 一种用于校准读取数据选通门控的方法，包括以下步骤：（A）执行粗调定时调整，其被配置为确定产生无效数据的粗略延迟设置，（B）执行配置成调整中等延迟设置的中等定时调整， 检测到有效数据之前的粗延迟设置，（C）执行精细定时调整，其被配置为调整介质延迟设置和精细延迟设置，直到检测到有效数据，并且（D）将半个周期添加到由 粗调，中等和精细延迟设置。

    Bit error testing and training in double data rate (DDR) memory system
    4.
    发明授权
    Bit error testing and training in double data rate (DDR) memory system 有权
    双数据速率（DDR）存储器系统中的位错误测试和训练

    公开(公告)号：US09257200B2

    公开(公告)日：2016-02-09

    申请号：US13559741

    申请日：2012-07-27

    申请人： Dharmesh N. Bhakta ,  Derrick Butt ,  Curtis M. Webster

    发明人： Dharmesh N. Bhakta ,  Derrick Butt ,  Curtis M. Webster

    IPC分类号： G11C29/00 ,  G11C29/02 ,  G11C29/56 ,  G11C11/40

    CPC分类号： G11C29/022 ,  G11C11/40 ,  G11C29/56008 ,  G11C29/56012 ,  G11C2029/5602

    摘要： DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane.

    摘要翻译： 为双数据速率存储器系统提供DDR PHY接口位错误测试和训练。 集成电路包括提供位模式的位误差测试（BERT）控制器; 以及具有多个字节通道的物理接口。 第一字节通道通过环回路径连接到第二字节通道，并且BERT控制器写入使用回送路径获得的位模式来评估物理接口。 评估包括（i）验证位模式是否被正确地写入和读取; （ii）用于定位内部门信号的门训练过程; （iii）读取调平训练过程以定位选通信号的两个边缘; 和/或（iv）写入位去偏移训练过程以对准给定字节通道内的多个位。

    Programmable data strobe enable architecture for DDR memory applications
    5.
    发明申请
    Programmable data strobe enable architecture for DDR memory applications 有权
    可编程数据选通功能支持DDR存储器应用的架构

    公开(公告)号：US20060291302A1

    公开(公告)日：2006-12-28

    申请号：US11166292

    申请日：2005-06-24

    申请人： Hui-Yin Seto ,  Derrick Butt

    发明人： Hui-Yin Seto ,  Derrick Butt

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22

    摘要： An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.

    摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以包括多个第一多路复用器和一个或多个第二多路复用器，其被配置为响应于（i）输入使能信号，（ii）以第一数据速率操作的第一时钟信号和（ iii）多个第一选择信号。 多个第一多路复用器各自向一个或多个第二多路复用器中的每一个提供输出。 第二电路可以被配置为响应于（i）第一中间使能信号，（ii）以第二数据速率操作的第二时钟信号和（iii）第二选择信号来产生第二中间使能信号。 第三电路可以被配置为响应于（i）第二中间使能信号，（ii）控制输入信号和（iii）第三选择信号而产生第三中间​​使能信号。 第三中间使能信号可以被配置为控制存储器的读取操作。

    BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM
    6.
    发明申请
    BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM 有权
    双重数据速率（DDR）存储器系统中的位错误测试和培训

    公开(公告)号：US20140029364A1

    公开(公告)日：2014-01-30

    申请号：US13559741

    申请日：2012-07-27

    申请人： Dharmesh N. Bhakta ,  Derrick Butt ,  Curtis M. Webster

    发明人： Dharmesh N. Bhakta ,  Derrick Butt ,  Curtis M. Webster

    IPC分类号： G11C29/00

    CPC分类号： G11C29/022 ,  G11C11/40 ,  G11C29/56008 ,  G11C29/56012 ,  G11C2029/5602

    摘要： DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane.

    摘要翻译： 为双数据速率存储器系统提供DDR PHY接口位错误测试和训练。 集成电路包括提供位模式的位误差测试（BERT）控制器; 以及具有多个字节通道的物理接口。 第一字节通道通过环回路径连接到第二字节通道，并且BERT控制器写入使用回送路径获得的位模式来评估物理接口。 评估包括（i）验证位模式是否被正确地写入和读取; （ii）用于定位内部门信号的门训练过程; （iii）读取调平训练过程以定位选通信号的两个边缘; 和/或（iv）写入位去偏移训练过程以对准给定字节通道内的多个位。

    Macro cell for integrated circuit physical layer interface
    8.
    发明申请
    Macro cell for integrated circuit physical layer interface 有权
    宏单元用于集成电路物理层接口

    公开(公告)号：US20050229132A1

    公开(公告)日：2005-10-13

    申请号：US10810294

    申请日：2004-03-26

    申请人： Derrick Butt ,  Bruce Cochrane ,  Hui Seto ,  William Lau ,  Thomas McCarthy

    发明人： Derrick Butt ,  Bruce Cochrane ,  Hui Seto ,  William Lau ,  Thomas McCarthy

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with the IO buffer cells in the interface portion. The macro cell also includes an interface definition having a plurality of interface IO signal nets, which are routed to corresponding ones of the plurality of macro cell signal slots. The macro cell is adapted to be instantiated as a unit in the integrated circuit design.

    摘要翻译： 为具有输入 - 输出（IO）区域的集成电路设计提供宏单元，所述输入 - 输出（IO）区域具有与IO区域的接口部分的IO槽中的其它单元物理分散的多个IO缓冲单元。 宏小区包括物理分散以便与接口部分中的IO缓冲单元基本对齐的多个宏小区IO信号时隙。 宏小区还包括具有多个接口IO信号网络的接口定义，其被路由到多个宏小区信号时隙中的相应的一个。 宏单元适于在集成电路设计中被实例化为单元。