公开(公告)号：US20070287246A1

公开(公告)日：2007-12-13

申请号：US11377236

申请日：2006-03-15

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Seng ,  Roger Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

摘要： A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

摘要翻译： 一种用于制造具有至少两个栅极区域的半导体器件的方法。 该方法包括提供包括表面的基底区域。 另外，该方法包括通过至少将第一多个离子注入到衬底区域中并且通过至少将第二多个离子注入衬底区域而在衬底区域中形成漏极区域来在衬底区域中形成源极区域。 漏极区域和源极区域彼此分离。 此外，该方法包括在表面上沉积栅极层，并在表面上形成第一栅极区域和第二栅极区域。

公开(公告)号：US20070181917A1

公开(公告)日：2007-08-09

申请号：US11377936

申请日：2006-03-15

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Seng ,  Roger Lee

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/66484 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region.

摘要翻译： 具有至少两个栅极区域的半导体器件。 该器件包括：衬底区域，其包括表面，衬底区域中的源极区域和衬底区域中的漏极区域。 漏极区域和源极区域彼此分离。 此外，该器件包括表面上的第一栅极区域，表面上的第二栅极区域以及表面上以及第一栅极区域和第二栅极区域之间的绝缘区域。 第一栅极区域和第二栅极区域被绝缘区域分开。 第一栅极区域能够在衬底区域中形成第一沟道。 第一通道从源极区域到漏极区域。 第二栅极区域能够在衬底区域中形成第二沟道。 第二通道从源极区域到漏极区域。

公开(公告)号：US08513727B2

公开(公告)日：2013-08-20

申请号：US12892879

申请日：2010-09-28

申请人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

发明人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

摘要： Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.

摘要翻译： 具有低关断状态泄漏电流和优异的数据保持时间特性的非易失性存储器件。 本发明提供了一种包括堆叠的栅极鳍效应晶体管非易失性存储器结构，其包括第一导电类型的绝缘体上硅衬底和从绝缘体的上表面突出的鳍状有源区。 该结构还包括形成在翅片有源区上的隧道氧化物层和设置在隧道氧化物层和绝缘体的上表面上的第一栅电极。 另外，该结构包括形成在第一栅电极上的氧化物/氮化物/氧化物（ONO）复合层，形成在ONO复合层上的第二栅极，并且被图案化以限定ONO复合层的预定区域。 该结构还包括形成在第二栅电极的侧壁上的介质间隔物和形成在第二栅电极两侧的鳍有源区中的源/漏区。

公开(公告)号：US08614487B2

公开(公告)日：2013-12-24

申请号：US11377936

申请日：2006-03-15

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

IPC分类号： H01L29/66

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/66484 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region.

摘要翻译： 具有至少两个栅极区域的半导体器件。 该器件包括：衬底区域，其包括表面，衬底区域中的源极区域和衬底区域中的漏极区域。 漏极区域和源极区域彼此分离。 此外，该器件包括表面上的第一栅极区域，表面上的第二栅极区域以及表面上以及第一栅极区域和第二栅极区域之间的绝缘区域。 第一栅极区域和第二栅极区域被绝缘区域分开。 第一栅极区域能够在衬底区域中形成第一沟道。 第一通道从源极区域到漏极区域。 第二栅极区域能够在衬底区域中形成第二沟道。 第二通道从源极区域到漏极区域。

公开(公告)号：US20110163369A1

公开(公告)日：2011-07-07

申请号：US12892879

申请日：2010-09-28

申请人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

发明人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

摘要： Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.

摘要翻译： 具有低关断状态泄漏电流和优异的数据保持时间特性的非易失性存储器件。 本发明提供了一种包括堆叠的栅极鳍效应晶体管非易失性存储器结构，其包括第一导电类型的绝缘体上硅衬底和从绝缘体的上表面突出的鳍状有源区。 该结构还包括形成在翅片有源区上的隧道氧化物层和设置在隧道氧化物层和绝缘体的上表面上的第一栅电极。 另外，该结构包括形成在第一栅电极上的氧化物/氮化物/氧化物（ONO）复合层，形成在ONO复合层上的第二栅极，并且被图案化以限定ONO复合层的预定区域。 该结构还包括形成在第二栅电极的侧壁上的介质间隔物和形成在第二栅电极两侧的鳍有源区中的源/漏区。

公开(公告)号：US08093114B2

公开(公告)日：2012-01-10

申请号：US12549192

申请日：2009-08-27

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

IPC分类号： H01L29/72

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

摘要： A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

摘要翻译： 一种用于制造具有至少两个栅极区域的半导体器件的方法。 该方法包括提供包括表面的基底区域。 另外，该方法包括通过至少将第一多个离子注入到衬底区域中并且通过至少将第二多个离子注入衬底区域而在衬底区域中形成漏极区域来在衬底区域中形成源极区域。 漏极区域和源极区域彼此分离。 此外，该方法包括在表面上沉积栅极层，并在表面上形成第一栅极区域和第二栅极区域。

公开(公告)号：US20100087040A1

公开(公告)日：2010-04-08

申请号：US12549192

申请日：2009-08-27

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

摘要： A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

摘要翻译： 一种用于制造具有至少两个栅极区域的半导体器件的方法。 该方法包括提供包括表面的基底区域。 另外，该方法包括通过至少将第一多个离子注入到衬底区域中并且通过至少将第二多个离子注入衬底区域而在衬底区域中形成漏极区域来在衬底区域中形成源极区域。 漏极区域和源极区域彼此分离。 此外，该方法包括在表面上沉积栅极层，并在表面上形成第一栅极区域和第二栅极区域。

公开(公告)号：US07582517B2

公开(公告)日：2009-09-01

申请号：US11377236

申请日：2006-03-15

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

IPC分类号： H01L29/72

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

摘要： A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

摘要翻译： 一种用于制造具有至少两个栅极区域的半导体器件的方法。 该方法包括提供包括表面的基底区域。 另外，该方法包括通过至少将第一多个离子注入到衬底区域中并且通过至少将第二多个离子注入衬底区域而在衬底区域中形成漏极区域来在衬底区域中形成源极区域。 漏极区域和源极区域彼此分离。 此外，该方法包括在表面上沉积栅极层，并在表面上形成第一栅极区域和第二栅极区域。

公开(公告)号：US08969108B2

公开(公告)日：2015-03-03

申请号：US13881723

申请日：2011-02-10

申请人： Deyuan Xiao ,  Richard Rugin Chang

发明人： Deyuan Xiao ,  Richard Rugin Chang

IPC分类号： H01L29/06 ,  H01L33/64 ,  H01L33/00 ,  H01L21/20

CPC分类号： H01L33/385 ,  H01L21/2007 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/62 ,  H01L33/641

摘要： A light emitting diode (LED) and a forming method thereof are provided. The method for forming the LED includes: providing a semiconductor substrate (20) and a sapphire substrate (30) respectively, wherein a first bonding layer (21) is formed on the silicon substrate (20), and a sacrificial layer (32), an LED die (33) and a second bonding layer (35) are formed in turn on the sapphire substrate (30); bonding the first bonding layer (21) and the second bonding layer (35); removing the sacrificial layer (32) and lifting off the sapphire substrate (30). The method increases the effective lighting area of the LED, improves heat radiation, and enhances lighting efficiency.

摘要翻译： 提供一种发光二极管（LED）及其形成方法。 形成LED的方法包括：分别提供半导体衬底（20）和蓝宝石衬底（30），其中在硅衬底（20）上形成第一接合层（21）和牺牲层（32）， 依次在蓝宝石衬底（30）上形成LED管芯（33）和第二接合层（35）; 接合第一接合层（21）和第二接合层（35）; 去除牺牲层（32）并提起蓝宝石衬底（30）。 该方法增加了LED的有效照明面积，改善了散热，提高了照明效率。

公开(公告)号：US08833431B2

公开(公告)日：2014-09-16

申请号：US13059634

申请日：2010-12-30

申请人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Qing Rao

发明人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Qing Rao

IPC分类号： B22D17/00

CPC分类号： C22C21/00 ,  B22D17/00 ,  C22C1/026 ,  C22C1/1036 ,  C22C26/00 ,  F21V29/85 ,  H01L23/3733 ,  H01L23/3736 ,  H01L33/641 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2933/0075 ,  H01L2924/00

摘要： The present invention discloses an aluminum alloy material, which is made of raw material of aluminum alloy. The raw material of aluminum alloy consists of the following constituents by percentage of weight: graphene: 0.1%˜1%, carbon nano tube: 1%˜5%, the rest being Al. The aluminum alloy material of the present invention has a good performance of heat dissipation, the thermal conductivity is higher than 200 W/m. Meanwhile, the present invention further provides a method of manufacturing aluminum alloy backboard, in which method, the raw material of aluminum alloy is heated and melted in a heating furnace, afterwards, the raw material of aluminum alloy after melting is formed into an aluminum alloy backboard by die-casting, in this way, the utilization rate of material is increased and the manufacturing cost of the backboard is reduced.

摘要翻译： 本发明公开了一种由铝合金原料制成的铝合金材料。 铝合金原料由以下重量百分比组成：石墨烯：0.1％〜1％，碳纳米管：1％〜5％，其余为Al。 本发明的铝合金材料具有良好的散热性能，导热系数高于200W / m。 同时，本发明还提供一种制造铝合金背板的方法，其中将铝合金原料在加热炉中加热熔化，之后将熔融后的铝合金原料形成为铝合金 通过压铸，通过这种方式，材料的利用率提高，背板的制造成本降低。