公开(公告)号：US20190308133A1

公开(公告)日：2019-10-10

申请号：US16376214

申请日：2019-04-05

申请人： Sunder Ramachandran ,  James Ott ,  Mahendra Ladharam Joshi ,  Pejman Kazempoor ,  Grant Lynn Hartman ,  Lily Jiang ,  Matthew L. George

发明人： Sunder Ramachandran ,  James Ott ,  Mahendra Ladharam Joshi ,  Pejman Kazempoor ,  Grant Lynn Hartman ,  Lily Jiang ,  Matthew L. George

IPC分类号： B01D53/14 ,  B01D53/18

摘要： A method of removing impurities from formation fluids includes introducing a formation fluid into a first end of a first tubular, directing the formation fluid along a first flow path toward a second end of the first tubular, redirecting the formation fluid along a second flow path defined by a second tubular arranged radially outwardly of the first flow path toward the first end, spraying a treatment fluid along the first flow path into the formation fluid, and directing a treated formation fluid through an outlet fluidically connected to the second flow path.

公开(公告)号：US20130157449A1

公开(公告)日：2013-06-20

申请号：US13686483

申请日：2012-11-27

申请人： JUNZHU CAO ,  LILY JIANG ,  CINDY LI ,  CREEK ZHU

发明人： JUNZHU CAO ,  LILY JIANG ,  CINDY LI ,  CREEK ZHU

IPC分类号： H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/82345 ,  H01L21/823842

摘要： A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.

摘要翻译： 提供一种用于形成金属栅极的方法。 在该方法中，提供具有第一区域和第二区域的基板。 在基板上形成虚拟门结构和ILD层。 去除虚拟门结构的虚拟门，分别在两个区域内形成开口。 工作功能层分别形成以覆盖开口。 在功函数层上形成金属层，然后进行CMP处理，直到ILD层露出，从而同时在两个区域内形成金属栅极。 对金属层仅执行一个CMP工艺，从而可以减少ILD层的过度抛光，并且可以更精确地控制金属栅极的厚度。

公开(公告)号：US08679923B2

公开(公告)日：2014-03-25

申请号：US13686483

申请日：2012-11-27

申请人： Junzhu Cao ,  Lily Jiang ,  Cindy Li ,  Creek Zhu

发明人： Junzhu Cao ,  Lily Jiang ,  Cindy Li ,  Creek Zhu

IPC分类号： H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/82345 ,  H01L21/823842

摘要： A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.

摘要翻译： 提供一种用于形成金属栅极的方法。 在该方法中，提供具有第一区域和第二区域的基板。 在基板上形成虚拟门结构和ILD层。 去除虚拟门结构的虚拟门，分别在两个区域内形成开口。 工作功能层分别形成以覆盖开口。 在功函数层上形成金属层，然后进行CMP处理，直到ILD层露出，从而同时在两个区域内形成金属栅极。 对金属层仅执行一个CMP工艺，从而可以减少ILD层的过度抛光，并且可以更精确地控制金属栅极的厚度。

公开(公告)号：US08513727B2

公开(公告)日：2013-08-20

申请号：US12892879

申请日：2010-09-28

申请人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

发明人： Deyuan Xiao ,  Lily Jiang ,  Gary Chen ,  Roger Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

摘要： Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.

摘要翻译： 具有低关断状态泄漏电流和优异的数据保持时间特性的非易失性存储器件。 本发明提供了一种包括堆叠的栅极鳍效应晶体管非易失性存储器结构，其包括第一导电类型的绝缘体上硅衬底和从绝缘体的上表面突出的鳍状有源区。 该结构还包括形成在翅片有源区上的隧道氧化物层和设置在隧道氧化物层和绝缘体的上表面上的第一栅电极。 另外，该结构包括形成在第一栅电极上的氧化物/氮化物/氧化物（ONO）复合层，形成在ONO复合层上的第二栅极，并且被图案化以限定ONO复合层的预定区域。 该结构还包括形成在第二栅电极的侧壁上的介质间隔物和形成在第二栅电极两侧的鳍有源区中的源/漏区。

公开(公告)号：US08105898B2

公开(公告)日：2012-01-31

申请号：US12647362

申请日：2009-12-24

申请人： Lily Jiang ,  Meng Feng Tsai ,  Jian Guang Chang

发明人： Lily Jiang ,  Meng Feng Tsai ,  Jian Guang Chang

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/302 ,  H01L21/31

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/3212 ,  H01L21/84 ,  H01L29/66825

摘要： A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

摘要翻译： 提供了一种用于制造闪存器件的方法，例如NAND，NOR。 该方法包括提供半导体衬底。 该方法包括形成覆盖多个浮动栅结构的第二多晶硅层，以形成设置在第二多晶硅层上的上表面。 上表面具有第一凹陷区域和第二凹陷区域。 该方法包括沉积覆盖上表面的电介质材料以填充第一凹陷区域和第二凹陷区域以形成第二上表面区域并覆盖第一升高区域，第二升高区域和第三升高区域。 该方法使第二上表面区域进行化学机械抛光工艺以除去第一升高区域，第二升高区域和第三升高区域，从而形成没有填充材料的基本上平坦化的第二多晶硅层。

公开(公告)号：US08105897B2

公开(公告)日：2012-01-31

申请号：US12647359

申请日：2009-12-24

申请人： Lily Jiang ,  Meng Feng Tsai ,  Jiang Guang Chang

发明人： Lily Jiang ,  Meng Feng Tsai ,  Jiang Guang Chang

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/302 ,  H01L21/31

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/3212 ,  H01L21/84 ,  H01L29/66825

摘要： A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

摘要翻译： 提供了一种用于制造闪存器件的方法，例如NAND，NOR。 该方法包括提供半导体衬底。 该方法包括形成覆盖多个浮动栅结构的第二多晶硅层，以形成设置在第二多晶硅层上的上表面。 上表面具有第一凹陷区域和第二凹陷区域。 该方法包括沉积覆盖上表面的光致抗蚀剂材料以填充第一凹陷区域和第二凹陷区域以形成第二上表面区域并覆盖第一升高区域，第二升高区域和第三升高区域。 该方法使第二上表面区域进行化学机械抛光工艺以除去第一升高区域，第二升高区域和第三升高区域，从而形成没有填充材料的基本上平坦化的第二多晶硅层。

公开(公告)号：US08097508B2

公开(公告)日：2012-01-17

申请号：US12647369

申请日：2009-12-24

申请人： Lily Jiang ,  Meng Feng Tsai ,  Jian Guang Chang

发明人： Lily Jiang ,  Meng Feng Tsai ,  Jian Guang Chang

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/302 ,  H01L21/31

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/3212 ,  H01L21/84 ,  H01L29/66825

摘要： A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

摘要翻译： 提供了一种用于制造闪存器件的方法，例如NAND，NOR。 该方法包括提供半导体衬底。 该方法包括形成覆盖多个浮动栅结构的第二多晶硅层，以形成设置在第二多晶硅层上的上表面。 上表面具有第一凹陷区域和第二凹陷区域。 该方法包括沉积覆盖上表面的掺杂电介质材料以填充第一凹陷区域和第二凹陷区域以形成第二上表面区域并覆盖第一升高区域，第二升高区域和第三升高区域。 该方法使第二上表面区域进行化学机械抛光工艺以除去第一升高区域，第二升高区域和第三升高区域，从而形成没有填充材料的基本上平坦化的第二多晶硅层。

公开(公告)号：US20100190329A1

公开(公告)日：2010-07-29

申请号：US12647369

申请日：2009-12-24

申请人： LILY JIANG ,  MENG FENG CAI ,  JAIN GUANG CHANG

发明人： LILY JIANG ,  MENG FENG CAI ,  JAIN GUANG CHANG

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/304

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/3212 ,  H01L21/84 ,  H01L29/66825

摘要： A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

摘要翻译： 提供了一种用于制造闪存器件的方法，例如NAND，NOR。 该方法包括提供半导体衬底。 该方法包括形成覆盖多个浮动栅结构的第二多晶硅层，以形成设置在第二多晶硅层上的上表面。 上表面具有第一凹陷区域和第二凹陷区域。 该方法包括沉积覆盖上表面的掺杂电介质材料以填充第一凹陷区域和第二凹陷区域以形成第二上表面区域并覆盖第一升高区域，第二升高区域和第三升高区域。 该方法使第二上表面区域进行化学机械抛光工艺以除去第一升高区域，第二升高区域和第三升高区域，从而形成没有填充材料的基本上平坦化的第二多晶硅层。

公开(公告)号：US06855809B2

公开(公告)日：2005-02-15

申请号：US10753910

申请日：2004-01-07

申请人： Dinesh O. Shah ,  George J. Dawson ,  A. Scott Muerhoff ,  Lily Jiang ,  Robin A. Gutierrez ,  Thomas P. Leary ,  Suresh Desai ,  James L. Stewart

发明人： Dinesh O. Shah ,  George J. Dawson ,  A. Scott Muerhoff ,  Lily Jiang ,  Robin A. Gutierrez ,  Thomas P. Leary ,  Suresh Desai ,  James L. Stewart

IPC分类号： G01N33/543 ,  C07K14/18 ,  C12N1/15 ,  C12N1/19 ,  C12N1/21 ,  C12N5/10 ,  C12N15/09 ,  C12P21/04 ,  G01N21/76 ,  G01N33/576 ,  C07K14/00 ,  A61K39/00 ,  C07H21/00 ,  C07K14/08 ,  C12N15/62

CPC分类号： C07K14/005 ,  C12N2770/24222 ,  G01N33/5767 ,  G01N2469/10 ,  G01N2469/20

摘要： The subject invention relates to methods for the simultaneous detection of Hepatitis C Virus (HCV) antigens as well as antibodies produced in response to HCV antigens. Furthermore, the subject invention allows one to detect antigens in the early, acute stage of infection, even prior to the development of antibodies, thereby allowing for early detection of infected blood and blood products, thus improving the safety of the blood supply.

摘要翻译： 本发明涉及同时检测丙型肝炎病毒（HCV）抗原以及响应HCV抗原产生的抗体的方法。 此外，本发明允许在感染的早期，急性期中检测抗原，甚至在抗体发生之前，从而允许早期检测感染的血液和血液制品，从而提高血液供应的安全性。

公开(公告)号：US08105899B2

公开(公告)日：2012-01-31

申请号：US12647367

申请日：2009-12-24

申请人： Lily Jiang ,  Meng Feng Tsai ,  Jian Guang Chang

发明人： Lily Jiang ,  Meng Feng Tsai ,  Jian Guang Chang

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/302 ,  H01L21/31

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/3212 ,  H01L21/84 ,  H01L29/66825

摘要： A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method forms at least one dielectric spacer within the first recessed region and at least one dielectric spacer within the second recessed region to form a resulting surface region, and subjects the resulting surface region to a chemical mechanical polishing process to cause formation of a substantially planarized second polysilicon layer free from the dielectric material.

摘要翻译： 提供了一种用于制造闪存器件的方法，例如NAND，NOR。 该方法包括提供半导体衬底。 该方法包括形成覆盖多个浮动栅结构的第二多晶硅层，以形成设置在第二多晶硅层上的上表面。 上表面具有第一凹陷区域和第二凹陷区域。 该方法包括沉积覆盖上表面的电介质材料以填充第一凹陷区域和第二凹陷区域以形成第二上表面区域并覆盖第一升高区域，第二升高区域和第三升高区域。 该方法在第一凹陷区域内形成至少一个电介质间隔物，以及在第二凹陷区域内形成至少一个电介质间隔物，以形成所得表面区域，并使得到的表面区域进行化学机械抛光工艺，以形成基本平坦化的 第二多晶硅层不含介电材料。