公开(公告)号：US20090286393A1

公开(公告)日：2009-11-19

申请号：US12467035

申请日：2009-05-15

Applicant: Leo Mathew ,  Dharmesh Jawarani

Inventor： Leo Mathew ,  Dharmesh Jawarani

IPC: H01L21/3205

CPC classification number: H01L31/1804 ,  H01L31/1896 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.

Abstract translation: 形成电子器件的方法可以包括形成与包含半导体材料的衬底的一侧相邻的图案化层。 该方法还可以包括从衬底分离半导体层和图案化层，其中半导体层是衬底的一部分。

公开(公告)号：US07544576B2

公开(公告)日：2009-06-09

申请号：US11192968

申请日：2005-07-29

Applicant: Dharmesh Jawarani ,  Chun-Li Liu ,  Marius K. Orlowski

Inventor： Dharmesh Jawarani ,  Chun-Li Liu ,  Marius K. Orlowski

IPC: H01L21/40

CPC classification number: H01L29/665 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.

Abstract translation: 半导体制造方法包括形成覆盖衬底的栅极模块。 使用栅极模块作为掩模在衬底中蚀刻凹陷。 阻挡层沉积在晶片上并进行各向异性蚀刻以在源极/漏极凹槽的侧壁上形成屏障“窗帘”。 沉积金属层，其中金属层与凹部内的半导体接触。 将晶片退火以选择性地形成硅化物。 金属相对于阻挡结构材料的扩散率比金属相对于半导体材料的扩散率小一个数量级。 蚀刻的凹槽可以包括再入口侧壁。 金属层可以是镍层，阻挡层可以是氮化钛层。 可以在覆盖半导体衬底的凹部中形成硅或硅锗外延结构。

公开(公告)号：US20070197011A1

公开(公告)日：2007-08-23

申请号：US11360318

申请日：2006-02-22

Applicant: Anadi Srivastava ,  Paul Grudowski ,  Dharmesh Jawarani ,  Rode Mora

Inventor： Anadi Srivastava ,  Paul Grudowski ,  Dharmesh Jawarani ,  Rode Mora

IPC: H01L21/4763 ,  H01L21/3205

CPC classification number: H01L21/76895 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6653

Abstract: A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor substrate (202) is provided which has a gate (209) disposed thereon and which has a spacer (219) disposed adjacent to the gate. The spacer is subjected to a recess etch which exposes a lateral portion of the gate. An implant region (215) is then created adjacent to the spacer, and a layer of silicide (225) is formed which extends over the exposed lateral portion of the gate.

Abstract translation: 提供了一种制造硅化栅（209）的方法。 根据该方法，提供一种半导体衬底（202），其具有设置在其上的栅极（209），并且具有邻近栅极设置的间隔物（219）。 间隔件进行凹口蚀刻，露出栅极的侧面部分。 然后在间隔物附近产生注入区域（215），并且形成一层硅化物（225），其在栅极的暴露侧面部分上延伸。

公开(公告)号：US20070173002A1

公开(公告)日：2007-07-26

申请号：US11339953

申请日：2006-01-26

Applicant: Mark Hall ,  Dharmesh Jawarani ,  Mehul Shroff ,  Edward Travis

Inventor： Mark Hall ,  Dharmesh Jawarani ,  Mehul Shroff ,  Edward Travis

IPC: H01L21/338 ,  H01L21/4763

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (100) of the T-shaped structure (84) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract translation: 半导体工艺和设备提供由多晶硅结构（10）和多晶硅间隔物（80,82）形成并且具有较窄的底部尺寸（例如，等于或低于40nm）的T形结构（84）和较大的顶部关键 尺寸（例如，在40nm以上），使得硅化物可以在至少T形结构的上部区域（100）中由第一材料（例如CoSi 2 N 2）形成（ 84），而不会导致由于在较小临界尺寸下某些硅化物可能发生的附聚和空隙引起的增加的电阻。

公开(公告)号：US20050112829A1

公开(公告)日：2005-05-26

申请号：US10718892

申请日：2003-11-21

Applicant: Dharmesh Jawarani ,  Nigel Cave ,  Michael Rendon

Inventor： Dharmesh Jawarani ,  Nigel Cave ,  Michael Rendon

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6656

Abstract: In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.

Abstract translation: 在半导体器件中，相对较深的锗注入和激活之前，镍沉积镍硅化镍形成之前。 锗的激活导致植入物区域中的晶格常数在背景衬底（其优选为硅）的晶格常数上增加。 效果是，如此改变的晶格避免形成二硅化镍。 结果是避免了硅化镍尖峰。

公开(公告)号：US08043888B2

公开(公告)日：2011-10-25

申请号：US12016733

申请日：2008-01-18

Applicant: Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

Inventor： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

IPC: H01L21/44

CPC classification number: H01L45/1675 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

Abstract translation: 形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。 形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。 当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。 当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

公开(公告)号：US20100227475A1

公开(公告)日：2010-09-09

申请号：US12784984

申请日：2010-05-21

Applicant: Leo Mathew ,  Dharmesh Jawarani

Inventor： Leo Mathew ,  Dharmesh Jawarani

IPC: H01L21/44

CPC classification number: H01L21/26506 ,  H01L31/022425 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/0312 ,  H01L31/03682 ,  H01L31/03762 ,  H01L31/03765 ,  H01L31/068 ,  H01L31/1864 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed.

Abstract translation: 形成电子器件的方法可以包括通过电化学工艺在包括半导体材料的衬底的侧面上形成金属层。 该方法还可以包括在距离侧面一定距离处将分离增强物质引入衬底中，并且将半导体层和金属层与衬底分离，其中半导体层是衬底的一部分。 在一个具体的实施方案中，分离增强物质可以结合到金属层中并移动到基底中，并且在具体实施方案中，可以将分离增强物质注入到基底中。 在另一个实施例中，可以使用这两种技术。 在另一实施例中，可以执行双面处理。

公开(公告)号：US20090162966A1

公开(公告)日：2009-06-25

申请号：US12004534

申请日：2007-12-21

Applicant: Dharmesh Jawarani ,  Vinod Kumar Agarwal

Inventor： Dharmesh Jawarani ,  Vinod Kumar Agarwal

IPC: H01L33/00

CPC classification number: H01L31/022425 ,  Y02E10/50

Abstract: A semiconductor device is formed on a low cost substrate 312 onto which is deposited a metal film 314 that serves as an intermediate bonding layer with a transferred film 324 of semiconducting material from a bulk semiconductor substrate 322. The metal film forms an intermetallic compound such as a silicide 316 and functions as a bonding agent between the low cost substrate and the semiconducting substrate, as a back surface field for reflection of minority carriers, and as a textured optical reflector of photons. The silicide also forms a low resistivity back-side ohmic contact with the semiconductor layer. This results in a low cost, flexible, high efficiency, thin film solar cell device.

Abstract translation: 半导体器件形成在低成本衬底312上，其上沉积有用作中间结合层的金属膜314，其具有来自体半导体衬底322的半导体材料的转移膜324.金属膜形成金属间化合物，例如 硅化物316并且用作低成本衬底和半导体衬底之间的结合剂，作为用于少数载流子的反射的背表面场，以及作为光子的纹理光学反射器。 硅化物也与半导体层形成低电阻率的背面欧姆接触。 这导致了低成本，灵活，高效率的薄膜太阳能电池装置。

公开(公告)号：US20070059911A1

公开(公告)日：2007-03-15

申请号：US11226826

申请日：2005-09-14

Applicant: Dharmesh Jawarani ,  John Alvis ,  Michael Harrison ,  Leo Mathew ,  John Moore ,  Rode Mora

Inventor： Dharmesh Jawarani ,  John Alvis ,  Michael Harrison ,  Leo Mathew ,  John Moore ,  Rode Mora

IPC: H01L21/3205

CPC classification number: H01L21/28518 ,  H01L21/2855

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.

Abstract translation: 半导体制造工艺包括形成覆盖在晶片（101）的半导体衬底（104）上的栅极电介质（114）上的栅电极（112）和包括垂直部分（118）的衬垫电介质层（116） 栅电极和覆盖在半导体衬底（104）的上表面上的水平部分（117）。 邻近垂直部分（118）并且覆盖衬里介电层（116）的水平部分（117）形成间隔物（108）。 在形成间隔物（108）之后，去除衬里电介质层（116）的暴露部分以形成被延伸间隔物（108）覆盖的衬里电介质结构（126）。 然后将延伸垫片（108）回蚀刻以露出或揭开衬垫介质结构（126）的四肢。 在蚀刻回间隔物（108）之前，金属（130）可以溅射沉积在晶片（101）上，准备形成硅化物（134）。 在蚀刻之后，晶片（101）可以浸入食人鱼溶液中并用氩气的RF溅射（140）清洁。

公开(公告)号：US07105429B2

公开(公告)日：2006-09-12

申请号：US10797222

申请日：2004-03-10

Applicant: Dharmesh Jawarani

Inventor： Dharmesh Jawarani

IPC: H01L21/3205

CPC classification number: H01L21/28518 ,  H01L21/321 ,  H01L29/665

Abstract: A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal silicide regions to source, gate and drain terminals of the transistor. The low temperature inhibits lateral encroachment. Unsilicided portions of the metal are removed and followed by an ion implant of an element, such as nitrogen, that diffuses into the metal silicide regions. A second anneal at a higher temperature than the first anneal is completed wherein the implanted nitrogen ions prevent lateral encroachment of metal silicide.

Abstract translation: 一种方法抑制金属硅化物侵入晶体管中的沟道区域，该晶体管使用金属硅化物作为其端子的电接触。 金属层沉积在晶体管上。 作为低温退火的第一退火形成金属硅化物区域到晶体管的源极，栅极和漏极端子。 低温抑制侧向侵入。 除去金属的未硅化部分，然后进行扩散到金属硅化物区域中的诸如氮的元素的离子注入。 在比第一退火更高的温度下进行第二退火，其中注入的氮离子防止金属硅化物的横向侵入。