公开(公告)号：US08472258B2

公开(公告)日：2013-06-25

申请号：US13269425

申请日：2011-10-07

Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US08324092B2

公开(公告)日：2012-12-04

申请号：US12652517

申请日：2010-01-05

Applicant: Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

Inventor： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC: H01L21/00

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract translation: 提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的差异而引入的离子的渗透问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和 缩放MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：US20120026798A1

公开(公告)日：2012-02-02

申请号：US13269425

申请日：2011-10-07

Applicant: Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C16/10

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US08076709B2

公开(公告)日：2011-12-13

申请号：US12873679

申请日：2010-09-01

Applicant: Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

Inventor： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC: H01L29/792 ,  G11C16/04

CPC classification number: G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Abstract translation: 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US08064261B2

公开(公告)日：2011-11-22

申请号：US12787158

申请日：2010-05-25

Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅结构的半导体非易失性存储器件中进行热孔注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US07863131B2

公开(公告)日：2011-01-04

申请号：US11189078

申请日：2005-07-26

Applicant: Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

Inventor： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42344

Abstract: Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x

Abstract translation: 用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。 在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独辅助图案。 通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。 考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。 如果与选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2×（t + d ）。

公开(公告)号：US07671404B2

公开(公告)日：2010-03-02

申请号：US11589095

申请日：2006-10-30

Applicant: Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

Inventor： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC: H01L29/94

CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US07636253B2

公开(公告)日：2009-12-22

申请号：US12354867

申请日：2009-01-16

Applicant: Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: G11C11/34

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract translation: 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US20070201272A1

公开(公告)日：2007-08-30

申请号：US11797164

申请日：2007-05-01

Applicant: Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: G11C16/04

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract translation: 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US20100203697A1

公开(公告)日：2010-08-12

申请号：US12763402

申请日：2010-04-20

Applicant: Digh HISAMOTO ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

Inventor： Digh HISAMOTO ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/792

Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

Abstract translation: 本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。 在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。 为了克服这个问题，本发明的集成半导体非易失性存储装置被配置成使得具有不同存储器栅极长度的存储单元集成在同一芯片上。 这允许以高速读取设备并重新编程增加的次数。