公开(公告)号：US07180135B1

公开(公告)日：2007-02-20

申请号：US10951695

申请日：2004-09-29

申请人： Dimitris E. Ioannou ,  Souvick Mitra ,  Akram Salman

发明人： Dimitris E. Ioannou ,  Souvick Mitra ,  Akram Salman

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L27/1203

摘要： Disclosed is a Silicon-On-Insulator (SOI) Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) logic family composed of ratioed logic with intrinsically “on” symmetric fully depleted double-gate (DG) SOI MOSFET load(s) and asymmetric fully depleted double gate MOSFET driver(s).

摘要翻译： 公开了一种由本质上“对称”全耗尽双栅极（DG）SOI MOSFET负载和不对称的比例逻辑组成的绝缘体上硅绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）逻辑系列 完全耗尽的双栅极MOSFET驱动器。

公开(公告)号：US20060201705A1

公开(公告)日：2006-09-14

申请号：US11433721

申请日：2006-05-12

申请人： Akram Salman ,  Warren Farnworth ,  Alan Wood ,  J. Brooks ,  Eugene Cloud

发明人： Akram Salman ,  Warren Farnworth ,  Alan Wood ,  J. Brooks ,  Eugene Cloud

IPC分类号： H05K1/18

CPC分类号： H05K3/4007 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/095 ,  H05K3/321 ,  H05K3/325 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10696 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

摘要： A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

公开(公告)号：US20120161232A1

公开(公告)日：2012-06-28

申请号：US13339020

申请日：2011-12-28

申请人： Farzan Farbiz ,  Akram Salman

发明人： Farzan Farbiz ,  Akram Salman

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H01L27/0277

摘要： An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.

摘要翻译： 集成电路包含具有二极管隔离DENMOS晶体管的电压保护结构，其具有接近二极管的保护元件和DENMOS晶体管。 保护元件包括耦合到地的有源区域。 二极管阳极连接到I / O焊盘。 二极管阴极连接到DENMOS漏极。 DENMOS源接地。 还公开了形成集成电路的过程。

公开(公告)号：US20090001472A1

公开(公告)日：2009-01-01

申请号：US11771565

申请日：2007-06-29

申请人： Akram Salman ,  Stephen Beebe

发明人： Akram Salman ,  Stephen Beebe

IPC分类号： H01L23/62 ,  H01L21/336

CPC分类号： H01L27/0255

摘要： A method for fabricating a semiconductor device is provided. According to this method, a first gate electrode and a second gate electrode are formed overlying a first portion of a silicon substrate, and ions of a first conductivity-type are implanted into a second portion of the silicon substrate to define a first conductivity-type diode region within the silicon substrate. Ions of a second conductivity-type are implanted into a third portion of the silicon substrate to define a second conductivity-type diode region within the silicon substrate. During one of the steps of implanting ions of the first conductivity-type and implanting ions of the second conductivity-type, ions are also implanted into at least part of the first portion to define a separation region within the first portion. The separation region splits the first portion into a first well device region and a second well device region. The separation region is formed in series between the first well device region and the second well device region.

摘要翻译： 提供一种制造半导体器件的方法。 根据该方法，在硅衬底的第一部分上形成第一栅电极和第二栅极，将第一导电类型的离子注入到硅衬底的第二部分中以限定第一导电型 硅衬底内的二极管区域。 将第二导电类型的离子注入到硅衬底的第三部分中以在硅衬底内限定第二导电型二极管区。 在植入第二导电类型的第一导电类型的离子和注入第二导电类型的离子的步骤之一中，离子也被注入到第一部分的至少一部分中以在第一部分内限定分离区域。 分离区域将第一部分分成第一阱器件区域和第二阱器件区域。 分离区域在第一阱器件区域和第二阱器件区域之间串联形成。

公开(公告)号：US07791102B2

公开(公告)日：2010-09-07

申请号：US11549923

申请日：2006-10-16

申请人： Akram Salman ,  Stephen Beebe

发明人： Akram Salman ,  Stephen Beebe

IPC分类号： H01L27/07

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N+-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.

摘要翻译： 提供了用于保护半导体器件免受静电放电事件的方法和装置。 静电放电保护装置包括硅衬底，设置在硅衬底内的P +型阳极区域和与P +型阳极区域串联设置在硅衬底内的N阱器件区域。 第一P阱器件区域与第一N阱器件区域串联设置在硅衬底内，并且N +型阴极区域设置在硅衬底内。 栅电极至少基本上覆盖在硅衬底的第一N阱和P阱器件区域上。

公开(公告)号：US20080087962A1

公开(公告)日：2008-04-17

申请号：US11549923

申请日：2006-10-16

申请人： Akram Salman ,  Stephen Beebe

发明人： Akram Salman ,  Stephen Beebe

IPC分类号： H01L23/62 ,  H01L21/8238

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N+-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.

摘要翻译： 提供了用于保护半导体器件免受静电放电事件的方法和装置。 静电放电保护器件包括设置在硅衬底内的硅衬底，P + +型阳极区域和设置在硅衬底内的N阱器件区域，该N阱器件区域与P < +阳极区域。 第一P阱器件区域设置在与第一N阱器件区域串联的硅衬底内，并且N + +型阴极区域设置在硅衬底内。 栅电极至少基本上覆盖在硅衬底的第一N阱和P阱器件区域上。

公开(公告)号：US08013393B2

公开(公告)日：2011-09-06

申请号：US11771565

申请日：2007-06-29

申请人： Akram Salman ,  Stephen Beebe

发明人： Akram Salman ,  Stephen Beebe

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： A method for fabricating a semiconductor device is provided. According to this method, a first gate electrode and a second gate electrode are formed overlying a first portion of a silicon substrate, and ions of a first conductivity-type are implanted into a second portion of the silicon substrate to define a first conductivity-type diode region within the silicon substrate. Ions of a second conductivity-type are implanted into a third portion of the silicon substrate to define a second conductivity-type diode region within the silicon substrate. During one of the steps of implanting ions of the first conductivity-type and implanting ions of the second conductivity-type, ions are also implanted into at least part of the first portion to define a separation region within the first portion. The separation region splits the first portion into a first well device region and a second well device region. The separation region is formed in series between the first well device region and the second well device region.

摘要翻译： 提供一种制造半导体器件的方法。 根据该方法，在硅衬底的第一部分上形成第一栅电极和第二栅极，将第一导电类型的离子注入到硅衬底的第二部分中以限定第一导电型 硅衬底内的二极管区域。 将第二导电类型的离子注入到硅衬底的第三部分中以在硅衬底内限定第二导电型二极管区。 在植入第二导电类型的第一导电类型的离子和注入第二导电类型的离子的步骤之一中，离子也被注入到第一部分的至少一部分中以在第一部分内限定分离区域。 分离区域将第一部分分成第一阱器件区域和第二阱器件区域。 分离区域在第一阱器件区域和第二阱器件区域之间串联形成。