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    Semiconductor processing methods for forming electrical contacts
    1.
    发明申请
    Semiconductor processing methods for forming electrical contacts 失效
    用于形成电触头的半导体加工方法

    公开(公告)号：US20050224981A1

    公开(公告)日：2005-10-13

    申请号：US10822030

    申请日：2004-04-08

    申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

    发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

    IPC分类号： H01L21/288 ,  H01L21/768 ,  B05D3/00

    CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

    摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

    Methods of Forming Semiconductor Structures
    4.
    发明申请
    Methods of Forming Semiconductor Structures 有权
    形成半导体结构的方法

    公开(公告)号：US20080102596A1

    公开(公告)日：2008-05-01

    申请号：US11968281

    申请日：2008-01-02

    申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

    发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

    IPC分类号： H01L21/02 ,  H01L21/4763

    CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

    摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

    Semiconductor structures
    9.
    发明申请
    Semiconductor structures 有权
    半导体结构

    公开(公告)号：US20060003583A1

    公开(公告)日：2006-01-05

    申请号：US11188235

    申请日：2005-07-22

    申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

    发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

    IPC分类号： H01L21/44

    CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to, the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

    摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

    Method for forming controlled geometry hardmasks including subresolution elements
    10.
    发明授权
    Method for forming controlled geometry hardmasks including subresolution elements 有权
    用于形成受控几何硬掩模的方法，包括分解元件

    公开(公告)号：US07473644B2

    公开(公告)日：2009-01-06

    申请号：US10883215

    申请日：2004-07-01

    申请人： Richard H. Lane ,  Fred Fishburn

    发明人： Richard H. Lane ,  Fred Fishburn

    IPC分类号： H01L21/00 ,  H01L21/44

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088

    摘要： Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.

    摘要翻译： 在诸如硅晶片或石英衬底之类的衬底上形成硬掩模材料的准确的对称横截面间隔物的方法，用于形成用于形成集成电路的精确的子分辨特征。 所得到的对称硬掩模间隔物与其对称的上部可用于精确地蚀刻底层基底中的良好限定的高纵横比特征。 一些公开的方法还能够同时形成具有常规和亚分辨率尺寸的各种尺寸的硬掩模结构，以使得能够蚀刻下面的衬底中的不同尺寸的结构特征。