公开(公告)号：US07713817B2

公开(公告)日：2010-05-11

申请号：US11968281

申请日：2008-01-02

申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

IPC分类号： H01L21/8242

CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

公开(公告)号：US07402094B2

公开(公告)日：2008-07-22

申请号：US10116243

申请日：2002-04-04

申请人： Dinesh Chopra ,  Gundu Sabde

发明人： Dinesh Chopra ,  Gundu Sabde

IPC分类号： B24B1/00 ,  C09K3/14

CPC分类号： B24B37/0056 ,  B24B9/065 ,  B24B37/042 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  H01L21/3212 ,  H01L21/7684 ,  Y10T29/49156

摘要： Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

摘要翻译： 平面化解决方案及其使用方法，使用固定磨料平面化垫从基板表面去除氮化钛。 平面化溶液采用蚀刻剂溶液或氧化溶液的形式。 蚀刻剂溶液是含有蚀刻剂和缓冲液的水溶液。 蚀刻剂含有对氮化钛有选择性的一种或多种蚀刻剂。 氧化溶液是含有氧化剂和缓冲液的水溶液。 氧化剂含有一种或多种对氮化钛有选择性的氧化剂。 在任一溶液中，即蚀刻剂或氧化溶液中，缓冲液含有一种或多种缓冲剂。 根据本发明平坦化的氮化钛层可以用于集成电路的制造以及利用这种集成电路的各种装置。

公开(公告)号：US07129160B2

公开(公告)日：2006-10-31

申请号：US10230602

申请日：2002-08-29

申请人： Dinesh Chopra

发明人： Dinesh Chopra

IPC分类号： H01L21/4763

CPC分类号： H01L21/3213 ,  B23H5/08 ,  C25F3/02 ,  C25F3/30 ,  C25F7/00 ,  H01L21/32115 ,  H01L21/32125 ,  H01L21/32134 ,  H01L21/7684

摘要： A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

摘要翻译： 一种用于从微电子衬底同时去除导电材料的方法和装置。 根据本发明的一个实施例的方法包括使微电子衬底的表面与电解液接触，微电子衬底具有第一和第二不同的导电材料。 该方法还可以包括通过选择电解液的pH来控制第一导电材料的第一开路电位和第二导电材料的第二开路电位之间的差。 该方法还可以包括通过使变化的电信号通过电解液和导电材料同时去除第一和第二导电材料的至少一部分。 因此，可以减少和/或消除两种导电材料之间的电偶相互作用的影响。

公开(公告)号：US07094699B2

公开(公告)日：2006-08-22

申请号：US10838047

申请日：2004-05-03

申请人： Bradley J. Howard ,  Dinesh Chopra

发明人： Bradley J. Howard ,  Dinesh Chopra

IPC分类号： H01L21/302

CPC分类号： H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76844 ,  H01L21/76888

摘要： A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

公开(公告)号：US06997781B2

公开(公告)日：2006-02-14

申请号：US10116585

申请日：2002-04-04

申请人： Dinesh Chopra ,  Gundu Sabde

发明人： Dinesh Chopra ,  Gundu Sabde

IPC分类号： B24B1/00

CPC分类号： B24B37/0056 ,  B24B9/065 ,  B24B37/042 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  H01L21/3212 ,  H01L21/7684 ,  Y10T29/49156

摘要： Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

公开(公告)号：US20060009136A1

公开(公告)日：2006-01-12

申请号：US11215787

申请日：2005-08-30

申请人： Dinesh Chopra ,  Gundu Sabde

发明人： Dinesh Chopra ,  Gundu Sabde

IPC分类号： B24B1/00

CPC分类号： B24B37/0056 ,  B24B9/065 ,  B24B37/042 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  H01L21/3212 ,  H01L21/7684 ,  Y10T29/49156

摘要： Titanium nitride layers planarized may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits. Planarizing solutions may be used for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents.

公开(公告)号：US20060003675A1

公开(公告)日：2006-01-05

申请号：US11215711

申请日：2005-08-30

申请人： Dinesh Chopra ,  Gundu Sabde

发明人： Dinesh Chopra ,  Gundu Sabde

IPC分类号： B24B1/00

CPC分类号： B24B37/0056 ,  B24B9/065 ,  B24B37/042 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  H01L21/3212 ,  H01L21/7684 ,  Y10T29/49156

摘要： Titanium nitride layers planarized may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits. Planarizing solutions may be used for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents.

摘要翻译： 平面化的氮化钛层可以用于集成电路的制造以及利用这种集成电路的各种装置。 平面化解决方案可用于使用固定磨料平面化垫从衬底的表面去除氮化钛。 平面化溶液采用蚀刻剂溶液或氧化溶液的形式。 蚀刻剂溶液是含有蚀刻剂和缓冲液的水溶液。 蚀刻剂含有对氮化钛有选择性的一种或多种蚀刻剂。 氧化溶液是含有氧化剂和缓冲液的水溶液。 氧化剂含有一种或多种对氮化钛有选择性的氧化剂。 在任一溶液中，即蚀刻剂或氧化溶液中，缓冲液含有一种或多种缓冲剂。

公开(公告)号：US20050224981A1

公开(公告)日：2005-10-13

申请号：US10822030

申请日：2004-04-08

申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred Fishburn

IPC分类号： H01L21/288 ,  H01L21/768 ,  B05D3/00

CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

公开(公告)号：US20050009318A1

公开(公告)日：2005-01-13

申请号：US10916751

申请日：2004-08-11

申请人： Dinesh Chopra ,  Fred Fishburn

发明人： Dinesh Chopra ,  Fred Fishburn

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76886 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48847 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01072 ,  H01L2924/01327 ,  H01L2924/05042 ,  H01L2924/14 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

摘要： A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer. An integrated circuit includes a semiconductive substrate, a layer comprising a first metal over the substrate, and a layer of alloy material within the first metal comprising layer. The alloy material layer may comprise the first metal and a second metal different from the first metal. The alloy material may be an intermetallic. A conductive connection may be formed on the alloy layer.

摘要翻译： 导电连接形成方法包括在基板上形成包括第一金属的第一层，并在第一层上形成包含不同于第一金属的第二金属的第二层。 可以将第一层的至少一部分转变成包含第一和第二金属的合金材料。 可以对合金材料形成导电连接。 与第一金属相比，合金材料可能不太容易形成金属氧化物。 作为示例，转换第一层可以包括退火第一层和第二层。 示例性的第一金属包括铜，并且示例性的第二金属包括铝，钛，钯，镁或两种或更多种这样的金属。 合金材料可以是金属间化合物。 可以向合金层形成导电连接。 集成电路包括半导体衬底，在衬底上包括第一金属的层以及在第一金属包含层内的合金材料层。 合金材料层可以包括第一金属和不同于第一金属的第二金属。 合金材料可以是金属间化合物。 可以在合金层上形成导电连接。

公开(公告)号：US06759330B2

公开(公告)日：2004-07-06

申请号：US10295536

申请日：2002-11-15

申请人： Dinesh Chopra ,  Kevin G. Donohoe ,  Cem Basceri

发明人： Dinesh Chopra ,  Kevin G. Donohoe ,  Cem Basceri

IPC分类号： H01L2144

CPC分类号： H01L21/28079 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76879 ,  H01L28/91 ,  H01L29/66583

摘要： In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.