公开(公告)号：US20130032793A1

公开(公告)日：2013-02-07

申请号：US13367061

申请日：2012-02-06

申请人： Do-Hyun KIM ,  Yoon Ho KHANG ,  Dong-Hoon LEE ,  Sang Ho PARK ,  Se Hwan YU ,  Cheol Kyu KIM ,  Yong-Su LEE ,  Sung-Haeng CHO ,  Chong Sup CHANG ,  Dong Jo KIM ,  Jung Kyu LEE

发明人： Do-Hyun KIM ,  Yoon Ho KHANG ,  Dong-Hoon LEE ,  Sang Ho PARK ,  Se Hwan YU ,  Cheol Kyu KIM ,  Yong-Su LEE ,  Sung-Haeng CHO ,  Chong Sup CHANG ,  Dong Jo KIM ,  Jung Kyu LEE

IPC分类号： H01L29/786 ,  H01L21/20

CPC分类号： H01L27/124 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

摘要： Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

摘要翻译： 提供了一种薄膜晶体管阵列面板。 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：设置在基板上的栅极布线层; 设置在所述栅极布线层上的氧化物半导体层; 以及数据布线层，其设置在所述氧化物半导体层上，所述数据布线层包括包含铜的主布线层和设置在所述主布线层上并包括铜合金的覆盖层。

公开(公告)号：US20120126233A1

公开(公告)日：2012-05-24

申请号：US13078790

申请日：2011-04-01

申请人： Chong Sup CHANG ,  Yoon Ho KHANG ,  Hyung Jun KIM ,  Se Hwan YU ,  Sang Ho PARK ,  Su-Hyoung KANG ,  Myoung Geun CHA ,  Young Ki SHIN ,  Ji Seon LEE

发明人： Chong Sup CHANG ,  Yoon Ho KHANG ,  Hyung Jun KIM ,  Se Hwan YU ,  Sang Ho PARK ,  Su-Hyoung KANG ,  Myoung Geun CHA ,  Young Ki SHIN ,  Ji Seon LEE

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/42384

摘要： Provided is a thin film transistor array panel. A thin film transistor array panel according to an exemplary embodiment includes a gate wire having a first region where the gate line is disposed, and a second region where the gate electrode is disposed, and a thickness of the gate wire formed in the first region is greater than the thickness of the gate wire that is formed in the second region.

摘要翻译： 提供了一种薄膜晶体管阵列面板。 根据示例性实施例的薄膜晶体管阵列面板包括栅极线，栅极线具有设置栅极线的第一区域和设置栅电极的第二区域，并且形成在第一区域中的栅极线的厚度为 大于在第二区域中形成的栅极线的厚度。

公开(公告)号：US20130032794A1

公开(公告)日：2013-02-07

申请号：US13367076

申请日：2012-02-06

申请人： Yong Su LEE ,  Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG

发明人： Yong Su LEE ,  Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG

IPC分类号： H01L29/786 ,  B82Y99/00

CPC分类号： H01L29/458 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/7869

摘要： Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.

摘要翻译： 提供了一种薄膜晶体管和薄膜晶体管阵列阵列。 薄膜晶体管包括：基板; 设置在所述基板上的栅电极; 设置在所述基板上并与所述栅电极部分重叠的半导体层; 源电极和漏电极相对于半导体层的沟道区彼此分开; 设置在所述栅电极和所述半导体层之间的绝缘层; 以及设置在所述半导体层和所述源电极之间以及所述半导体层和所述漏电极之间的阻挡层，其中所述阻挡层包括石墨烯。 基于用于半导体层的材料的类型提供欧姆接触。

公开(公告)号：US20120138920A1

公开(公告)日：2012-06-07

申请号：US13099108

申请日：2011-05-02

申请人： Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG ,  Sang Ho PARK ,  Su-Hyoung KANG

发明人： Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG ,  Sang Ho PARK ,  Su-Hyoung KANG

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L27/1225 ,  H01L29/7869

摘要： A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：设置在绝缘基板上的栅电极; 栅极绝缘层，设置在栅电极上; 设置在所述栅极绝缘层上的氧化物半导体; 设置在所述氧化物半导体上的阻挡层; 设置在所述阻挡层上的源电极和漏电极; 钝化层，其设置在所述源电极和所述漏电极上; 以及设置在钝化层上的像素电极。 阻挡层包括由源电极和漏电极覆盖的第一部分和未被源电极和漏电极覆盖的第二部分，并且第一部分和第二部分包括不同的材料。

公开(公告)号：US20120086678A1

公开(公告)日：2012-04-12

申请号：US13163528

申请日：2011-06-17

申请人： Chong Sup CHANG ,  Yoonho Khang ,  Changoh Jeong ,  Sehwan Yu ,  Sangho Park ,  Su-Hyoung Kang ,  Hyungjun Kim ,  Honglong Ning ,  Jinho Hwang ,  Myounggeun Cha ,  Youngki Shin

发明人： Chong Sup CHANG ,  Yoonho Khang ,  Changoh Jeong ,  Sehwan Yu ,  Sangho Park ,  Su-Hyoung Kang ,  Hyungjun Kim ,  Honglong Ning ,  Jinho Hwang ,  Myounggeun Cha ,  Youngki Shin

IPC分类号： G09G5/00 ,  H05K3/10

CPC分类号： G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136295 ,  G02F2201/123 ,  Y10T29/49155

摘要： A wire is provided on an insulating substrate to have a first thickness in a first area and a second thickness smaller than the first thickness in a second area except for the first area. A display apparatus includes the wire. The wire is formed by forming a first conductive layer and a second conductive layer on the insulating substrate and etching the first and second conductive layers using photoresist layer patterns having different thicknesses.

摘要翻译： 在除了第一区域之外的第二区域中，在绝缘基板上设置有具有在第一区域中的第一厚度和小于第一厚度的第二厚度的布线。 显示装置包括线。 通过在绝缘基板上形成第一导电层和第二导电层并使用具有不同厚度的光致抗蚀剂层图案蚀刻第一和第二导电层来形成导线。