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公开(公告)号：US06015991A
公开(公告)日：2000-01-18
申请号：US820401
申请日：1997-03-12
IPC分类号： H01L21/027 , H01L21/266 , H01L21/3213 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/78 , H01L29/02
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/32139 , H01L29/42376 , H01L29/66545 , H01L29/66659 , H01L29/7835 , H01L21/0274
摘要： Disclosed is an asymmetric field effect transistor which comprises a first region serving as source, a second region serving as drain, a thin gate oxide and a gate electrode. The gate electrode is asymmetric and one of its sidewalls is sloped. The second region extends underneath said sloped sidewall. The part of said second region which extends underneath said gate electrode is less doped than the remaining part of said second region. Furthermore, said second region has a sloped junction edge underneath said gate electrode.
摘要翻译： 公开了一种非对称场效应晶体管，其包括用作源极的第一区域，用作漏极的第二区域，薄栅极氧化物和栅电极。 栅电极是不对称的，其侧壁之一是倾斜的。 第二区域在所述倾斜侧壁的下方延伸。 在所述栅电极下方延伸的所述第二区域的部分比所述第二区域的剩余部分掺杂少。 此外，所述第二区域在所述栅电极下方具有倾斜的接合边缘。
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公开(公告)号：US06228745B1
公开(公告)日：2001-05-08
申请号：US09460134
申请日：1999-12-13
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S438/947
摘要： Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.
摘要翻译： 公开了一种半导体结构，其包括在半导体衬底中形成的源极注入和漏极注入的晶体管。 晶体管还包括栅电极，栅极氧化物和有源区。 源极注入和漏极注入位于所述有源区的相对侧，并且所述栅极氧化物和栅电极位于所述有源区的顶部。 晶体管还包括与所述有源区相邻的两个沟槽隔离，其中所述沟槽隔离位于所述有源区的相对侧，使得每个沟槽的侧壁用作与所述有源区的界面，所述沟槽的至少一个侧壁 用作与所述有源区的界面的隔离具有倾斜的90°至150°之间的斜率，所述沟槽隔离和源极注入和漏极注入在四个侧面上包围所述有源区。
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公开(公告)号：US06809372B2
公开(公告)日：2004-10-26
申请号：US09756177
申请日：2001-01-09
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.
摘要翻译： 闪速存储器和形成闪速存储器的方法包括在衬底上形成多晶硅字线，所述字线具有第一和第二侧壁，所述第一侧壁相对于所述衬底的表面是渐缩的，以具有倾斜角和 所述第二侧壁具有大于所述第一侧壁的倾斜角的倾斜角。 此后，在第二侧壁上形成多晶硅间隔物，同时去除第一侧壁上的多晶硅。 多晶硅间隔物形成浮动栅极，其通过第二侧壁在多个侧面上被包围。
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公开(公告)号：US06252271B1
公开(公告)日：2001-06-26
申请号：US09097515
申请日：1998-06-15
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.
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公开(公告)号：US5985492A
公开(公告)日：1999-11-16
申请号：US10611
申请日：1998-01-22
IPC分类号： G03F1/28 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F1/28
摘要： A photomask and a method for using the photomask to make dimensionally controlled resist patterns are provided. A wafer having a resist coating thereon is exposed using the mask of the invention under specially controlled defocus conditions to provide the dimensionally controlled resist pattern profile. The mask which comprises multiple phase shifter means on one side of at least one of the light shielding patterns on the mask provides light passing through the mask having multiple phases on that side of the light shielding material which produces a dimensionally controlled resist pattern profile.
摘要翻译： 提供光掩模和使用光掩模来制造尺寸控制的抗蚀剂图案的方法。 在其上具有抗蚀剂涂层的晶片在特殊控制的散焦条件下使用本发明的掩模曝光以提供尺寸控制的抗蚀剂图案轮廓。 在掩模上的至少一个遮光图案的一侧包括多个移相器装置的掩模提供通过遮光材料的该侧的多个相位的光的光，其产生尺寸控制的抗蚀剂图形轮廓。
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公开(公告)号：US06407396B1
公开(公告)日：2002-06-18
申请号：US09339783
申请日：1999-06-24
IPC分类号： H01J37304
CPC分类号： G03F7/70625 , G03F7/70633 , H01J2237/2816 , H01L22/34
摘要： A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture. The second pattern also includes a feature having a second dimension identical to a second critical dimension of the second pattern formed in the corresponding second level.
摘要翻译： 一种用于测量半导体器件的多个图案的关键尺寸特征并且相对于另一个图案叠加测量一个图案的晶片度量结构。 测量可以通过计量系统的单一一维扫描来读取。 晶片计量结构包括形成在半导体器件的第一级中的至少第一尺寸的第一特征。 第一尺寸与在相应的第一层中形成的图案的第一临界尺寸相同。 根据本发明的晶片测量图案还包括形成在半导体器件的第二级中的第二尺寸的第二图案。 第二图案包括叠加在第一特征上的光圈。 孔径至少暴露出具有第一图案的临界尺寸的第一特征，从而使计量系统能够通过孔直接测量第一特征。 第二图案还包括具有与在相应的第二层中形成的第二图案的第二临界尺寸相同的第二尺寸的特征。
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7.发明授权Method and apparatus for critical dimension and tool resolution determination using edge width 失效使用边缘宽度确定关键尺寸和刀具分辨率的方法和装置
公开(公告)号：US5969273A
公开(公告)日：1999-10-19
申请号：US23059
申请日：1998-02-12
申请人： Charles N. Archie , Mark E. Lagus , Diana Nyyssonen, deceased , by Jeffrey Swing, legal representative , Eric P. Solecky , Donald C. Wheeler
发明人： Charles N. Archie , Mark E. Lagus , Diana Nyyssonen, deceased , by Jeffrey Swing, legal representative , Eric P. Solecky , Donald C. Wheeler
摘要： A method for monitoring a process in which a feature is formed on a substrate. A plurality of dimensions of the feature are measured using a tool. An edge width of the feature is calculated based on the plurality of dimensions. The edge width is used to determine whether the process is operating within a desired specification. The calculated edge width is compared to a baseline edge width measurement to determine a difference between them. The process is determined to be operating within the specification if the difference is less than a threshold value. If the difference is greater than or equal to the threshold value, the method determines whether the difference is caused by a change in resolution of the tool. A plurality of diagnostic measurements of the edge width may be performed. The tool is adjusted to have a respectively different focus for each respective one of the plurality of diagnostic measurements. The method includes determining that the difference between the calculated edge width and the baseline edge width is caused by a change in resolution of the tool if any one of the plurality of diagnostic measurements of the edge width differs from the baseline edge width by less than the threshold value. The method also includes determining that the process is not operating within the specification, if the difference is greater than or equal to the threshold value, and the difference is not caused by a change in resolution of the tool.
摘要翻译： 一种用于监测在基板上形成特征的工艺的方法。 使用工具测量特征的多个尺寸。 基于多个维度来计算特征的边缘宽度。 边缘宽度用于确定过程是否在所需规格内运行。 将计算的边缘宽度与基线边缘宽度测量进行比较，以确定它们之间的差异。 如果差小于阈值，则确定该过程在规范内操作。 如果差值大于或等于阈值，则该方法确定该差异是否由工具的分辨率的变化引起。 可以执行边缘宽度的多个诊断测量。 调整该工具以针对多个诊断测量中的每个相应的一个分别具有不同的焦点。 该方法包括确定所计算的边缘宽度与基线边缘宽度之间的差异是由工具的分辨率的变化引起的，如果边缘宽度的多个诊断测量中的任何一个与基线边缘宽度不同，小于 阈值。 该方法还包括如果差值大于或等于阈值，则确定该过程不在规范内操作，并且该差异不是由工具的分辨率改变引起的。
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