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公开(公告)号：US06015991A
公开(公告)日：2000-01-18
申请号：US820401
申请日：1997-03-12
IPC分类号： H01L21/027 , H01L21/266 , H01L21/3213 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/78 , H01L29/02
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/32139 , H01L29/42376 , H01L29/66545 , H01L29/66659 , H01L29/7835 , H01L21/0274
摘要： Disclosed is an asymmetric field effect transistor which comprises a first region serving as source, a second region serving as drain, a thin gate oxide and a gate electrode. The gate electrode is asymmetric and one of its sidewalls is sloped. The second region extends underneath said sloped sidewall. The part of said second region which extends underneath said gate electrode is less doped than the remaining part of said second region. Furthermore, said second region has a sloped junction edge underneath said gate electrode.
摘要翻译： 公开了一种非对称场效应晶体管，其包括用作源极的第一区域，用作漏极的第二区域，薄栅极氧化物和栅电极。 栅电极是不对称的，其侧壁之一是倾斜的。 第二区域在所述倾斜侧壁的下方延伸。 在所述栅电极下方延伸的所述第二区域的部分比所述第二区域的剩余部分掺杂少。 此外，所述第二区域在所述栅电极下方具有倾斜的接合边缘。
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公开(公告)号：US06228745B1
公开(公告)日：2001-05-08
申请号：US09460134
申请日：1999-12-13
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S438/947
摘要： Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.
摘要翻译： 公开了一种半导体结构，其包括在半导体衬底中形成的源极注入和漏极注入的晶体管。 晶体管还包括栅电极，栅极氧化物和有源区。 源极注入和漏极注入位于所述有源区的相对侧，并且所述栅极氧化物和栅电极位于所述有源区的顶部。 晶体管还包括与所述有源区相邻的两个沟槽隔离，其中所述沟槽隔离位于所述有源区的相对侧，使得每个沟槽的侧壁用作与所述有源区的界面，所述沟槽的至少一个侧壁 用作与所述有源区的界面的隔离具有倾斜的90°至150°之间的斜率，所述沟槽隔离和源极注入和漏极注入在四个侧面上包围所述有源区。
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公开(公告)号：US5985492A
公开(公告)日：1999-11-16
申请号：US10611
申请日：1998-01-22
IPC分类号： G03F1/28 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F1/28
摘要： A photomask and a method for using the photomask to make dimensionally controlled resist patterns are provided. A wafer having a resist coating thereon is exposed using the mask of the invention under specially controlled defocus conditions to provide the dimensionally controlled resist pattern profile. The mask which comprises multiple phase shifter means on one side of at least one of the light shielding patterns on the mask provides light passing through the mask having multiple phases on that side of the light shielding material which produces a dimensionally controlled resist pattern profile.
摘要翻译： 提供光掩模和使用光掩模来制造尺寸控制的抗蚀剂图案的方法。 在其上具有抗蚀剂涂层的晶片在特殊控制的散焦条件下使用本发明的掩模曝光以提供尺寸控制的抗蚀剂图案轮廓。 在掩模上的至少一个遮光图案的一侧包括多个移相器装置的掩模提供通过遮光材料的该侧的多个相位的光的光，其产生尺寸控制的抗蚀剂图形轮廓。
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公开(公告)号：US06407396B1
公开(公告)日：2002-06-18
申请号：US09339783
申请日：1999-06-24
IPC分类号： H01J37304
CPC分类号： G03F7/70625 , G03F7/70633 , H01J2237/2816 , H01L22/34
摘要： A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture. The second pattern also includes a feature having a second dimension identical to a second critical dimension of the second pattern formed in the corresponding second level.
摘要翻译： 一种用于测量半导体器件的多个图案的关键尺寸特征并且相对于另一个图案叠加测量一个图案的晶片度量结构。 测量可以通过计量系统的单一一维扫描来读取。 晶片计量结构包括形成在半导体器件的第一级中的至少第一尺寸的第一特征。 第一尺寸与在相应的第一层中形成的图案的第一临界尺寸相同。 根据本发明的晶片测量图案还包括形成在半导体器件的第二级中的第二尺寸的第二图案。 第二图案包括叠加在第一特征上的光圈。 孔径至少暴露出具有第一图案的临界尺寸的第一特征，从而使计量系统能够通过孔直接测量第一特征。 第二图案还包括具有与在相应的第二层中形成的第二图案的第二临界尺寸相同的第二尺寸的特征。
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公开(公告)号：US6132940A
公开(公告)日：2000-10-17
申请号：US213028
申请日：1998-12-16
申请人： Rebecca D. Mih , Franz X. Zach
发明人： Rebecca D. Mih , Franz X. Zach
CPC分类号： G03F7/2024 , G03F7/00 , G03F7/2022
摘要： A method of making at least one feature on an object having an upper surface, comprising the steps of:1. applying a layer of a photoresist having an initial thickness to the upper surface;2. exposing the layer of photoresist to a first dosage of light having a first intensity for a first predetermined period of time, such that at least a portion of the upper surface has a thickness that is at most equal to the initial thickness; and3. exposing the layer of photoresist to a second dosage of light having a second intensity for a second predetermined period of time, such that at least a subset of the portion of the upper surface exposed by the first dosage of light is exposed by the second dosage of light.
摘要翻译： 一种在具有上表面的物体上制造至少一个特征的方法，包括以下步骤：1.将具有初始厚度的光致抗蚀剂层施加到上表面; 2.将光致抗蚀剂层暴露于具有第一强度的第一剂量的光，持续第一预定时间段，使得上表面的至少一部分具有最大等于初始厚度的厚度; 以及3.将所述光致抗蚀剂层暴露于具有第二强度的第二剂量的光，持续第二预定时间段，使得由所述第一剂量的光暴露的所述上表面部分的至少一部分被所述第 第二剂量的光。
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公开(公告)号：US06448629B2
公开(公告)日：2002-09-10
申请号：US09354742
申请日：1999-07-29
申请人： Rebecca D. Mih , Kevin S. Petrarca
发明人： Rebecca D. Mih , Kevin S. Petrarca
IPC分类号： H01L2906
CPC分类号： H01L21/0332 , H01L21/76224 , H01L21/7684
摘要： A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.
摘要翻译： 第二或盖电介质层介于通常的或基底电介质层与半导体器件的金属电路层之间。 基极电介质层在半导体器件的非活性部分中具有多个凹部，盖电介质层的部分延伸以将盖电介质层与基底电介质层互锁，并且相对于（1）的剪切或撕裂 金属电路层作为金属电路层进行化学机械抛光，或（2）当金属电路层进行化学机械抛光时，从基极介电层获得硬掩模层。
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公开(公告)号：US06391703B1
公开(公告)日：2002-05-21
申请号：US09894336
申请日：2001-06-28
申请人： Nivo Rovedo , Chung H. Lam , Rebecca D. Mih
发明人： Nivo Rovedo , Chung H. Lam , Rebecca D. Mih
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.
摘要翻译： 包括嵌入式DRAM的逻辑电路通过同时形成将存储单元电容器与传输晶体管连接的带以及将逻辑晶体管源极和漏极与衬底隔离的埋入介质层来实现工艺集成。
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公开(公告)号：US06284574B1
公开(公告)日：2001-09-04
申请号：US09223979
申请日：1999-01-04
IPC分类号： H01L2148
CPC分类号： H01L23/36 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： A structure and process are described for facilitating the conduction of heat away from a semiconductor device. Thermally conductive planes and columns are incorporated within the back-end structure and around the interconnect outside the chip. A thermally conductive plane is formed by forming a first insulating layer on an underlying layer of the device; forming a recess in the insulating layer; filling the recess with a thermally conductive material to form a lateral heat-dissipating layer; planarizing the heat-dissipating layer to make the top surface thereof coplanar with the unrecessed portion of the insulating layer; and forming a second insulating layer on the first insulating layer and the heat-dissipating layer, thereby embedding the heat-dissipating layer between the first and second insulating layers. The heat-dissipating layer is electrically isolated from the underlying layer of the device, and preferably is electrically grounded.
摘要翻译： 描述了用于促进远离半导体器件的热传导的结构和工艺。 导热平面和列结合在后端结构中并且围绕芯片外的互连。 导热平面通过在器件的下层上形成第一绝缘层而形成; 在所述绝缘层中形成凹部; 用导热材料填充凹部以形成横向散热层; 使散热层平坦化，使其顶面与绝缘层的未加工部分共面; 以及在所述第一绝缘层和所述散热层上形成第二绝缘层，从而将所述散热层嵌入所述第一绝缘层和所述第二绝缘层之间。 散热层与器件的下层电隔离，优选电接地。
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公开(公告)号：US20120040277A1
公开(公告)日：2012-02-16
申请号：US13278571
申请日：2011-10-21
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
摘要： A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.
摘要翻译： 用于能够容纳标线的抛光工具的掩模版载体包括具有正面和反面的基板，固定在基板的正面的保持环，形成由刚性基板的正面限定的凹部和内部 固定环的边缘。 掩模垫在凹槽中支撑掩模版。 基板和标线垫具有一组匹配的对准的通孔，用于从底板和标线板之间的空间排出空气，并将空气供给到该空间，因此真空可以将该掩模版保持在适当的位置上 在真空条件下的掩模版载体和在压力下施加空气可以从掩模版载体喷出掩模版。
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公开(公告)号：US20080286660A1
公开(公告)日：2008-11-20
申请号：US11749384
申请日：2007-05-16
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
摘要： A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.
摘要翻译： 光学投影掩模版的制造方法采用镶嵌工艺。 第一特征凹槽被蚀刻到透射或透明的突出掩模掩模板中。 然后，特征凹部用包括用于吸收光化辐射的部分透射材料和/或辐射吸收体的辐射透射率改性材料研磨。 牺牲材料可以在填充凹部之前临时添加到凹部中，以提供与填充凹部的材料并置的间隙。 此后，去除牺牲材料。 然后将投影掩模平坦化，留下填充有透射率改性材料的特征凹部，以及任何期望的间隙。 投影面罩被平坦化，同时保持在用抛光工具和浆料抛光过程中将其固定在位置的夹具中。
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