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460 条记录 (耗时 0.034 秒)

    Flash memory structure using sidewall floating gate
    2.
    发明授权
    Flash memory structure using sidewall floating gate 失效
    闪存结构采用侧壁浮栅

    公开(公告)号：US06809372B2

    公开(公告)日：2004-10-26

    申请号：US09756177

    申请日：2001-01-09

    申请人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Donald C. Wheeler

    发明人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Donald C. Wheeler

    IPC分类号： H01L29788

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

    摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.

    摘要翻译： 闪速存储器和形成闪速存储器的方法包括在衬底上形成多晶硅字线，所述字线具有第一和第二侧壁，所述第一侧壁相对于所述衬底的表面是渐缩的，以具有倾斜角和 所述第二侧壁具有大于所述第一侧壁的倾斜角的倾斜角。 此后，在第二侧壁上形成多晶硅间隔物，同时去除第一侧壁上的多晶硅。 多晶硅间隔物形成浮动栅极，其通过第二侧壁在多个侧面上被包围。

    Dual work function gate conductors with self-aligned insulating cap
    4.
    发明授权
    Dual work function gate conductors with self-aligned insulating cap 失效
    具有自对准绝缘帽的双功能栅极导体

    公开(公告)号：US06274467B1

    公开(公告)日：2001-08-14

    申请号：US09327080

    申请日：1999-06-04

    申请人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

    发明人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

    IPC分类号： H01L2122

    CPC分类号： H01L21/28035 ,  H01L21/28052 ,  H01L21/32155 ,  H01L21/823842

    摘要： A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack includes a gate insulating layer formed on the substrate and a layer of polysilicon on top of the gate insulating layer. The polysilicon layer may be doped n-type remain intrinsic. A barrier layer is formed on top of the polysilicon layer and a dopant source layer is formed on top of the barrier layer. The barrier layer contains a p-type dopant. The gate stack is enclosed by an insulating cap so that a diffusion contact can be formed borderless to the gate. Activation of the dopant source layer to dope a polysilicon layer can be delayed until a desired time.

    摘要翻译： 提供一种具有自对准绝缘帽的双功能栅极导体及其形成方法。 在衬底中形成两个扩散区域，并且在扩散区域之间的衬底上形成栅叠层。 栅极堆叠包括形成在衬底上的栅极绝缘层和位于栅极绝缘层顶部的多晶硅层。 多晶硅层可以掺杂n型保持固有。 在多晶硅层的顶部形成阻挡层，并且在阻挡层的顶部上形成掺杂剂源层。 阻挡层含有p型掺杂剂。 栅极堆叠被绝缘盖封闭，使得扩散接触可以形成与栅极无边界。 激发掺杂剂源层以掺杂多晶硅层可以被延迟到期望的时间。

    High performance embedded DRAM technology with strained silicon
    7.
    发明授权
    High performance embedded DRAM technology with strained silicon 失效
    具有应变硅的高性能嵌入式DRAM技术

    公开(公告)号：US07262451B2

    公开(公告)日：2007-08-28

    申请号：US10541660

    申请日：2003-01-08

    申请人： Jack A. Mandelman ,  Jeffrey P. Gambino ,  Geng Wang

    发明人： Jack A. Mandelman ,  Jeffrey P. Gambino ,  Geng Wang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3081 ,  H01L27/10864

    摘要： Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

    摘要翻译： 半导体器件制造在同一衬底的应变层区域和无应变层的层中。 第一半导体器件，例如存储器单元，例如 在衬底的无应变层的区域中形成深沟槽存储单元。 在相同的衬底中选择性地形成应变层区域。 第二半导体器件（66,68,70），例如FET，例如， 一个MOSFET逻辑器件，形成在应变层区域中。

    Structure and method for dual gate oxidation for CMOS technology
    8.
    发明授权
    Structure and method for dual gate oxidation for CMOS technology 失效
    用于CMOS技术的双栅极氧化的结构和方法

    公开(公告)号：US06674134B2

    公开(公告)日：2004-01-06

    申请号：US09173430

    申请日：1998-10-15

    申请人： Wayne S. Berry ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Wayne S. Berry ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L2976

    CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823462

    摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

    摘要翻译： 本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接 其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成 相应较薄的中心区域。

    Transistors having independently adjustable parameters
    9.
    发明授权
    Transistors having independently adjustable parameters 有权
    晶体管具有可独立调节的参数

    公开(公告)号：US06501131B1

    公开(公告)日：2002-12-31

    申请号：US09359291

    申请日：1999-07-22

    申请人： Rama Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rajesh Rengarajan

    发明人： Rama Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rajesh Rengarajan

    IPC分类号： H01L2976

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823807 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66583

    摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.

    摘要翻译： 制造半导体器件如MOSFET的工艺规则被修改，以提供遵循常规栅极侧壁氧化步骤的双重功能掺杂，大大降低了热预算和硼渗透问题。 通过允许减小的间隙宽高比同时保持低的薄层电阻值的装置结构，热预算的关注进一步显着降低。 减小的间隙宽高比也放松了对高回流电介质材料的需要，并且还有助于使用倾斜的源漏（S-D）和晕轮植入物。 还提供了用于产生MOSFET沟道，横向掺杂分布的新型结构和工艺，其抑制短沟道效应，同时提供低S-D结电容和泄漏，以及对热载流子效应的抗扰性。 这也提供了减小接触柱对栅极导体电容的可能性，因为可以用氧化物栅极侧壁间隔物形成无边界接触。 结果，S-D结可以独立于栅极导体掺杂掺杂，更容易地允许各种MOSFET结构。

    Method of manufacturing a semiconductor device having a shallow trench isolating region
    10.
    发明授权
    Method of manufacturing a semiconductor device having a shallow trench isolating region 失效
    制造具有浅沟槽隔离区域的半导体器件的方法

    公开(公告)号：US06479368B1

    公开(公告)日：2002-11-12

    申请号：US09033067

    申请日：1998-03-02

    申请人： Jack A. Mandelman ,  Mutsuo Morikado ,  Herbert Ho ,  Jeffrey P. Gambino

    发明人： Jack A. Mandelman ,  Mutsuo Morikado ,  Herbert Ho ,  Jeffrey P. Gambino

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased. The method comprises forming a trench in a semiconductor substrate, for isolating elements, forming a nitride film on a surface of the trench, depositing mask material on an entire surface of the semiconductor substrate, filling the trench with the mask material, etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate, removing an exposed upper portion of the nitride film on the surface of the trench, removing the mask material from the trench, filling the trench with element-isolating material, thereby forming an element-isolating region, and forming a transistor in an element region isolated from another element region by the element-isolating region.

    摘要翻译： 一种制造半导体器件的方法，其中可以减少浅沟槽隔离中的凹陷的深度。 该方法包括在半导体衬底中形成沟槽，用于隔离元件，在沟槽的表面上形成氮化物膜，在半导体衬底的整个表面上沉积掩模材料，用掩模材料填充沟槽，蚀刻掩模材料 直到沟槽中的掩模材料的表面水平落在半导体衬底的表面之下，去除沟槽表面上暴露的氮化物膜的上部，从沟槽中去除掩模材料， 从而形成元件隔离区域，并且通过元件隔离区域在与另一个元件区域隔离的元件区域中形成晶体管。