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    Method for fabricating nonvolatile memory device
    1.
    发明授权
    Method for fabricating nonvolatile memory device 有权
    非易失性存储器件的制造方法

    公开(公告)号：US08735247B2

    公开(公告)日：2014-05-27

    申请号：US13204349

    申请日：2011-08-05

    申请人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

    发明人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L29/76

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

    摘要翻译： 公开了一种用于制造非易失性存储器件的方法。 该方法包括在半导体衬底上形成用于公共源极线的第一结构，第一结构沿着第一方向延伸，通过在半导体衬底上交替堆叠多个牺牲层和多个绝缘层来形成模具结构，形成 所述模具结构中的多个开口露出所述第一结构的一部分，以及在所述第一结构的第一侧形成第一存储单元串，以及在所述第一结构的第二相反侧形成第二存储单元串。 多个开口包括第一通孔和第二通孔，每个通孔穿过多个牺牲层和多个绝缘层，并且第一通孔和第二通孔重叠在一起 第一个方向。

    METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE
    2.
    发明申请
    METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE 有权
    用于制造非易失性存储器件的方法

    公开(公告)号：US20120052673A1

    公开(公告)日：2012-03-01

    申请号：US13204349

    申请日：2011-08-05

    申请人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

    发明人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

    摘要翻译： 公开了一种用于制造非易失性存储器件的方法。 该方法包括在半导体衬底上形成用于公共源极线的第一结构，第一结构沿着第一方向延伸，通过在半导体衬底上交替堆叠多个牺牲层和多个绝缘层来形成模具结构，形成 所述模具结构中的多个开口露出所述第一结构的一部分，以及在所述第一结构的第一侧形成第一存储单元串，以及在所述第一结构的第二相反侧形成第二存储单元串。 多个开口包括第一通孔和第二通孔，每个通孔穿过多个牺牲层和多个绝缘层，并且第一通孔和第二通孔重叠在一起 第一个方向。

    Vertical Memory Devices And Methods Of Manufacturing The Same
    4.
    发明申请
    Vertical Memory Devices And Methods Of Manufacturing The Same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20120098139A1

    公开(公告)日：2012-04-26

    申请号：US13246152

    申请日：2011-09-27

    申请人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

    发明人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

    IPC分类号： H01L23/48 ,  H01L21/44

    CPC分类号： H01L27/11582 ,  H01L29/7926

    摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

    摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线，字符串选择线（SSL）和触点。 通道包括垂直部分和水平部分。 垂直部分在基本上垂直于基板的顶表面的第一方向上延伸，并且水平部分连接到垂直部分并且平行于基板的顶表面。 GSL，字线和SSL沿着第一方向依次形成在通道的垂直部分的侧壁上，并且彼此间隔开。 触点位于基板上并电连接到通道的水平部分。

    Methods of manufacturing a vertical type semiconductor device
    5.
    发明授权
    Methods of manufacturing a vertical type semiconductor device 有权
    制造垂直型半导体器件的方法

    公开(公告)号：US08426304B2

    公开(公告)日：2013-04-23

    申请号：US13241316

    申请日：2011-09-23

    申请人： Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

    发明人： Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11582 ,  H01L27/105 ,  H01L27/11573 ,  H01L27/11575

    摘要： Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.

    摘要翻译： 制造半导体器件的方法包括在衬底的第一区域中形成停止层图案。 第一模具结构形成在与第一区域相邻的基板的第二区域中。 第一模具结构包括交替堆叠的第一牺牲图案和第一层间图案。 在第一模具结构和止挡层图案上形成第二模具结构。 第二模具结构包括交替堆叠的第二牺牲图案和第二层间图案。 第二模具结构部分地覆盖止挡层图案。 形成通道图案并通过第一模具结构和第二模具结构。

    Charge-trapping nonvolatile memory devices having gate structures therein with improved blocking layers
    6.
    发明授权
    Charge-trapping nonvolatile memory devices having gate structures therein with improved blocking layers 有权
    电荷捕获其中具有栅极结构的非易失性存储器件具有改进的阻挡层

    公开(公告)号：US08410542B2

    公开(公告)日：2013-04-02

    申请号：US12938006

    申请日：2010-11-02

    申请人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

    发明人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42324 ,  G11C16/0416 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

    摘要： Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer.

    摘要翻译： 非易失性存储器件包括衬底上的隧道绝缘层和隧道绝缘层上的电荷存储层。 电荷转移阻挡层设置在电荷存储层上。 电荷转移阻挡层形成为多层的复合物，其包括厚度为约至约的第一氧化物层。 该第一氧化物层直接形成在电荷存储层上。 电荷转移阻挡层包括在第一氧化物层上的第一电介质层。 电荷转移阻挡层还包括在第一介电层上的第二氧化物层和第二氧化物层上的第二介电层。 第一和第二电介质层分别相对于第一和第二氧化物层具有更高的介电常数。 存储单元包括电荷转移阻挡层上的导电电极。

    Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers
    7.
    发明申请
    Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers 有权
    具有门结构的非易失性存储器件在其中具有改进的阻挡层

    公开(公告)号：US20110101438A1

    公开(公告)日：2011-05-05

    申请号：US12938006

    申请日：2010-11-02

    申请人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

    发明人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/42324 ,  G11C16/0416 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

    摘要： Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer.

    摘要翻译： 非易失性存储器件包括衬底上的隧道绝缘层和隧道绝缘层上的电荷存储层。 电荷转移阻挡层设置在电荷存储层上。 电荷转移阻挡层形成为多层的复合物，其包括厚度为约至约的第一氧化物层。 该第一氧化物层直接形成在电荷存储层上。 电荷转移阻挡层包括在第一氧化物层上的第一电介质层。 电荷转移阻挡层还包括在第一介电层上的第二氧化物层和第二氧化物层上的第二介电层。 第一和第二电介质层分别相对于第一和第二氧化物层具有更高的介电常数。 存储单元包括电荷转移阻挡层上的导电电极。

    Vertical memory devices and methods of manufacturing the same
    8.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US09012974B2

    公开(公告)日：2015-04-21

    申请号：US13246152

    申请日：2011-09-27

    申请人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

    发明人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

    IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L27/115

    CPC分类号： H01L27/11582 ,  H01L29/7926

    摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

    摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线，字符串选择线（SSL）和触点。 通道包括垂直部分和水平部分。 垂直部分在基本上垂直于基板的顶表面的第一方向上延伸，并且水平部分连接到垂直部分并且平行于基板的顶表面。 GSL，字线和SSL沿着第一方向依次形成在通道的垂直部分的侧壁上，并且彼此间隔开。 触点位于基板上并电连接到通道的水平部分。