公开(公告)号：US08760192B2

公开(公告)日：2014-06-24

申请号：US13538035

申请日：2012-06-29

申请人： Dong-Ryul Chang ,  Hwa-Sook Shin ,  Hoon-Jin Bang

发明人： Dong-Ryul Chang ,  Hwa-Sook Shin ,  Hoon-Jin Bang

IPC分类号： H03K19/173

CPC分类号： H03K3/356165 ,  H03K19/1736

摘要： Provided is a programmable circuit. The programmable circuit includes a first path and a second path connected in parallel between a first voltage node and a second voltage node. The first path includes a first programmable element, a first node, a first pull-up transistor, a second node, and a first pull-down transistor connected in series between the first voltage node and the second voltage node. The second path includes a second programmable element, a third node, a second pull-up transistor, a fourth node, and a second pull-down transistor connected in series between the first and second voltage nodes. A gate electrode of the first pull-up transistor, a gate electrode of the first pull-down transistor, and the fourth node are electrically connected to one another. A gate electrode of the second pull-up transistor, a gate electrode of the second pull-down transistor, and the second node are electrically connected to one another.

摘要翻译： 提供了一个可编程电路。 可编程电路包括在第一电压节点和第二电压节点之间并联连接的第一路径和第二路径。 第一路径包括串联连接在第一电压节点和第二电压节点之间的第一可编程元件，第一节点，第一上拉晶体管，第二节点和第一下拉晶体管。 第二路径包括串联连接在第一和第二电压节点之间的第二可编程元件，第三节点，第二上拉晶体管，第四节点和第二下拉晶体管。 第一上拉晶体管的栅电极，第一下拉晶体管的栅电极和第四节点彼此电连接。 第二上拉晶体管的栅电极，第二下拉晶体管的栅电极和第二节点彼此电连接。

公开(公告)号：US09117655B2

公开(公告)日：2015-08-25

申请号：US13537692

申请日：2012-06-29

申请人： Dong-Ryul Chang ,  Hwa-Sook Shin

发明人： Dong-Ryul Chang ,  Hwa-Sook Shin

IPC分类号： H01L29/49 ,  H01L27/02 ,  H01L21/28 ,  H01L29/788 ,  H01L27/115

CPC分类号： H01L27/0207 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11526 ,  H01L29/7881

摘要： A semiconductor device includes a main active region provided in a semiconductor substrate and having a first side surface and a second side surface facing each other. A first auxiliary active region adjacent the first side surface of the main active region and spaced apart from the main active region by a first distance is provided. A second auxiliary active region adjacent the second side surface of the main active region and spaced apart from the main active region by the first distance is provided. A first conductive pattern crosses the main active region and includes first and second side portions facing each other. The first side portion of the conductive pattern is disposed between the first auxiliary active region and the main active region, and the second side portion of the conductive pattern is disposed between the second auxiliary active region and the main active region.

摘要翻译： 半导体器件包括设置在半导体衬底中并具有彼此面对的第一侧表面和第二侧表面的主有效区域。 提供了与主有效区域的第一侧表面相邻并且与主有效区域间隔开第一距离的第一辅助有源区。 提供了与主有效区域的第二侧表面相邻并且与主有效区域间隔开第一距离的第二辅助有源区。 第一导电图案与主活性区域交叉并且包括彼此面对的第一和第二侧部。 导电图案的第一侧部分设置在第一辅助有源区和主有源区之间，导电图案的第二侧部设置在第二辅助有源区和主有源区之间。

公开(公告)号：US08749022B2

公开(公告)日：2014-06-10

申请号：US13156371

申请日：2011-06-09

申请人： Dong-Ryul Chang ,  Hwa-Sook Shin

发明人： Dong-Ryul Chang ,  Hwa-Sook Shin

IPC分类号： H01L21/02

CPC分类号： H01L29/94 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/90 ,  H01L29/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode.

摘要翻译： 电容器装置包括：衬底，其包括具有第一导电类型的第一阱和施加于其上的第一电压;以及施加到其上的具有第二导电类型和第二电压的第二阱; 以及设置在所述第一阱的上部或所述第二阱的上部的栅电极，使得所述栅电极与所述第一阱或所述第二阱绝缘，其中所述电容器器件的电容包括第一电容 在第一阱和第二阱之间以及第一阱或第二阱和栅电极之间的第二电容。

公开(公告)号：US08247286B2

公开(公告)日：2012-08-21

申请号：US12712260

申请日：2010-02-25

申请人： Dong-Ryul Chang

发明人： Dong-Ryul Chang

IPC分类号： H01L21/8238

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836

摘要： One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

摘要翻译： 本文示例性描述的发明概念的一个实施例可以通常被表征为包括衬底内的隔离区域的半导体器件。 隔离区域可以限定有源区域。 有源区域可以包括与隔离区域和有源区域的界面相邻的边缘部分和由边缘部分包围的中心区域。 半导体器件还可以包括在有源区上的栅电极和隔离区。 栅极可以包括与有源区的中心部分重叠的中心栅极部分，与有源区域的边缘部分重叠的边缘栅极部分和第一导电类型的第一杂质区域在中心栅极部分内部和边缘外部 一部分。 半导体器件还可以包括设置在有源区和栅电极之间的栅极绝缘层。

公开(公告)号：US20100148252A1

公开(公告)日：2010-06-17

申请号：US12712260

申请日：2010-02-25

申请人： Dong-Ryul Chang

发明人： Dong-Ryul Chang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836

摘要： One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

摘要翻译： 本文示例性描述的发明概念的一个实施例可以通常被表征为包括衬底内的隔离区域的半导体器件。 隔离区域可以限定有源区域。 有源区域可以包括与隔离区域和有源区域的界面相邻的边缘部分和由边缘部分包围的中心区域。 半导体器件还可以包括在有源区上的栅电极和隔离区。 栅极可以包括与有源区的中心部分重叠的中心栅极部分，与有源区域的边缘部分重叠的边缘栅极部分和第一导电类型的第一杂质区域在中心栅极部分内部和边缘外部 一部分。 半导体器件还可以包括设置在有源区和栅电极之间的栅极绝缘层。

公开(公告)号：US20070158780A1

公开(公告)日：2007-07-12

申请号：US11634148

申请日：2006-12-06

申请人： Dong-Ryul Chang

发明人： Dong-Ryul Chang

IPC分类号： H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/42368

摘要： A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed on the active region of the semiconductor substrate. Trench insulating layers may be formed in the semiconductor substrate on and around edges of the gate pattern so as to be able to relieve an electrical field from the gate pattern. The depths of each of the trench insulating layers may be defined according to an operating voltage. Source and drain regions enclose the trench insulating layers and may be formed in the semiconductor substrate on both sides of the gate pattern. Therefore, the semiconductor integrated circuit device may have a higher integration density and may relieve an electrical field from the gate pattern.

摘要翻译： 提供了具有更高集成密度的半导体集成电路器件及其制造方法。 半导体集成电路器件可以包括限定有源区的半导体衬底中的沟槽隔离区域和用于更高电压并形成在半导体衬底的有源区上的栅极图案。 可以在栅极图案的边缘上和周围的半导体衬底中形成沟槽绝缘层，以便能够减轻来自栅极图案的电场。 每个沟槽绝缘层的深度可以根据工作电压来定义。 源极和漏极区域包围沟槽绝缘层，并且可以形成在栅极图案的两侧上的半导体衬底中。 因此，半导体集成电路器件可以具有更高的集成密度并且可以缓解来自栅极图案的电场。

公开(公告)号：US20070145477A1

公开(公告)日：2007-06-28

申请号：US11705354

申请日：2007-02-12

申请人： Tae-Jung Lee ,  Soo-Cheol Lee ,  Dong-Ryul Chang

发明人： Tae-Jung Lee ,  Soo-Cheol Lee ,  Dong-Ryul Chang

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0882 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

摘要翻译： 场效应晶体管包括形成在限定在衬底上的有源区的沟道区中的栅极。 源极形成在相邻地设置在栅极的第一侧面的有源区的第一表面部分处。 在有源区域的与栅极相对的第一表面部分的第二表面部分处形成漏极。 漏极具有从基板的表面部突出的突出部。

公开(公告)号：US20060284219A1

公开(公告)日：2006-12-21

申请号：US11441304

申请日：2006-05-25

申请人： Dong-Ryul Chang ,  Soo-Cheol Lee ,  Tae-Jung Lee ,  Hyeon-Cheol Kim

发明人： Dong-Ryul Chang ,  Soo-Cheol Lee ,  Tae-Jung Lee ,  Hyeon-Cheol Kim

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/823871

摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a semiconductor substrate, a transistor having a gate interconnection that extends in one direction on the semiconductor substrate and source/drain regions aligned in the gate interconnection and formed in the semiconductor substrate, and a diffusion-preventing metallic pattern extending on the gate interconnection in the same direction as the gate interconnection and which prevents ions from being diffused into the semiconductor substrate.

摘要翻译： 提供了一种半导体集成电路器件。 半导体集成电路器件包括半导体衬底，具有在半导体衬底上沿一个方向延伸的栅极互连的晶体管和在栅极互连中对准并形成在半导体衬底中的源/漏区，以及扩展防止金属图案延伸 在与栅极互连相同的方向上的栅极互连上，并且防止离子扩散到半导体衬底中。

公开(公告)号：US20050067662A1

公开(公告)日：2005-03-31

申请号：US10952105

申请日：2004-09-28

申请人： Tae-Jung Lee ,  Soo-Cheol Lee ,  Dong-Ryul Chang

发明人： Tae-Jung Lee ,  Soo-Cheol Lee ,  Dong-Ryul Chang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/08 ,  H01L29/94

CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0882 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

摘要翻译： 场效应晶体管包括形成在限定在衬底上的有源区的沟道区中的栅极。 源极形成在相邻地设置在栅极的第一侧面的有源区的第一表面部分处。 在有源区域的与栅极相对的第一表面部分的第二表面部分处形成漏极。 漏极具有从基板的表面部突出的突出部。

公开(公告)号：US20110303961A1

公开(公告)日：2011-12-15

申请号：US13076910

申请日：2011-03-31

申请人： Dong-Ryul Chang ,  Myoung-Kyu Park

发明人： Dong-Ryul Chang ,  Myoung-Kyu Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/11519

摘要： A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The to nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.

摘要翻译： 包括其中多个单元电池至少沿一个方向排列的单元阵列区域的非易失性存储器件包括形成在各个单元电池中的多个存储晶体管。 每个存储晶体管包括其中层叠有隧道绝缘层，浮栅，栅极间绝缘层和控制栅极的栅极图案，以及布置在栅极图案的相对侧上的第一和第二接合区域，其中栅极 图案沿单位单元在一个方向上分离。 非易失性存储器件还包括在一个方向上延伸并且布置在与控制栅极重叠的位置和多个第一触点的第一导电互连中，其中至少一个布置用于每个控制栅极连接 控制门和第一导电互连。