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    POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME
    1.
    发明申请
    POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME 有权
    掉电模式控制装置和具有该模式的DLL电路

    公开(公告)号：US20090121784A1

    公开(公告)日：2009-05-14

    申请号：US12175212

    申请日：2008-07-17

    申请人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

    发明人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

    IPC分类号： G05F1/10

    CPC分类号： G11C7/02 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C7/222

    摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

    摘要翻译： 断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率 下降模式信号和内部掉电信号。

    Power-down mode control apparatus and DLL circuit having the same
    3.
    发明授权
    Power-down mode control apparatus and DLL circuit having the same 有权
    掉电模式控制装置和DLL电路具有相同的功能

    公开(公告)号：US07868673B2

    公开(公告)日：2011-01-11

    申请号：US12698606

    申请日：2010-02-02

    申请人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

    发明人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

    IPC分类号： H03L7/06

    CPC分类号： G11C7/02 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C7/222

    摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

    摘要翻译： 断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率 下降模式信号和内部掉电信号。

    Power-down mode control apparatus and DLL circuit having the same
    4.
    发明授权
    Power-down mode control apparatus and DLL circuit having the same 有权
    掉电模式控制装置和DLL电路具有相同的功能

    公开(公告)号：US07683684B2

    公开(公告)日：2010-03-23

    申请号：US12175212

    申请日：2008-07-17

    申请人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

    发明人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

    IPC分类号： H03L7/06

    CPC分类号： G11C7/02 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C7/222

    摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

    摘要翻译： 断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率 下降模式信号和内部掉电信号。

    DLL circuit and method of controlling the same
    6.
    发明授权
    DLL circuit and method of controlling the same 有权
    DLL电路及其控制方法

    公开(公告)号：US07598783B2

    公开(公告)日：2009-10-06

    申请号：US11826401

    申请日：2007-07-16

    申请人： Dong-Suk Shin ,  Hyun-Woo Lee ,  Won-Joo Yun

    发明人： Dong-Suk Shin ,  Hyun-Woo Lee ,  Won-Joo Yun

    IPC分类号： H03L7/06

    CPC分类号： H03K5/133 ,  H03K5/1565 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03L7/0814 ,  H03L7/087

    摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.

    摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。 校正控制单元响应于占空比检测信号产生校正控制信号。 占空比校正单元校正内部的占空比。 响应于校正控制信号，从而输出参考时钟。

    DUTY CYCLE CORRECTING CIRCUIT AND METHOD
    7.
    发明申请
    DUTY CYCLE CORRECTING CIRCUIT AND METHOD 审中-公开
    占空比校正电路和方法

    公开(公告)号：US20090058483A1

    公开(公告)日：2009-03-05

    申请号：US12200747

    申请日：2008-08-28

    申请人： Dong-Suk Shin ,  Hyun-Woo Lee ,  Won-Joo Yun

    发明人： Dong-Suk Shin ,  Hyun-Woo Lee ,  Won-Joo Yun

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal.

    摘要翻译： 占空比校正电路包括检测输出时钟信号的占空比以输出占空比检测信号的占空比检测器，输出通过根据占空比检测信号可变地延迟输入信号而获得的延迟时钟信号的可变延迟单元， 以及脉冲宽度调制单元，当所述输入时钟信号和所述延迟时钟信号都处于高电平时，产生处于高电平的第一时钟信号，并且当所述第二时钟信号为 输入时钟信号和延迟时钟信号处于高电平，其中脉冲宽度调制单元选择性地输出第一时钟信号或第二时钟信号作为输出时钟信号。

    Semiconductor memory apparatus with a delay locked loop circuit
    8.
    发明授权
    Semiconductor memory apparatus with a delay locked loop circuit 有权
    具有延迟锁定环路的半导体存储装置

    公开(公告)号：US07605623B2

    公开(公告)日：2009-10-20

    申请号：US11824428

    申请日：2007-06-29

    申请人： Won-Joo Yun ,  Hyun-Woo Lee

    发明人： Won-Joo Yun ,  Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/095

    摘要： A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.

    摘要翻译： 一种半导体存储装置，包括：延迟线，被配置为延迟参考时钟;第一延迟块，被配置为延迟反馈时钟;第一相位比较器，被配置为将参考时钟与第一延迟块的输出进行比较;第二延迟块， 延迟参考时钟;第二相位比较器，被配置为将反馈时钟与第二延迟块的输出进行比较;延迟控制器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟线的延迟量， 延迟模型，被配置为延迟延迟线的输出通过建模的延迟时间以产生反馈时钟;以及锁定检测器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟控制器。

    Semiconductor memory device
    9.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20080054964A1

    公开(公告)日：2008-03-06

    申请号：US11819783

    申请日：2007-06-29

    申请人： Hyun-Woo Lee ,  Won-Joo Yun

    发明人： Hyun-Woo Lee ,  Won-Joo Yun

    IPC分类号： G11C8/00 ,  H03L7/06

    CPC分类号： G11C7/1072 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0818

    摘要： A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.

    摘要翻译： 半导体存储器件包括用于校正延迟锁定时钟信号的占空比的延迟锁定环路。 半导体存储器件包括延迟锁定电路，占空比校正电路和时钟同步电路。 延迟锁定电路通过将系统时钟延迟预定时间来输出延迟锁定时钟。 占空比校正电路通过校正延迟锁定时钟的占空比来输出第一时钟，其中延迟锁定时钟的高电平到低电平周期的比例根据第一时钟的第二边沿和 来自第一时钟的第二时钟的信号。 时钟同步电路将第一时钟的第一边沿与第二时钟的第一边沿同步。

    DLL circuit and method of controlling the same
    10.
    发明授权
    DLL circuit and method of controlling the same 有权
    DLL电路及其控制方法

    公开(公告)号：US07764096B2

    公开(公告)日：2010-07-27

    申请号：US12173728

    申请日：2008-07-15

    申请人： Hyun-Woo Lee ,  Won-Joo Yun

    发明人： Hyun-Woo Lee ,  Won-Joo Yun

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/0814

    摘要： A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.

    摘要翻译： 延迟锁定环（DLL）电路包括时钟信号划分单元，其可以将预定分频比除以参考时钟信号并产生除法时钟信号，该反馈环可以对分频时钟信号执行延迟锁定操作并产生 延迟时钟信号，半周期延迟单元，其可以将所述延迟时钟信号延迟所述基准时钟信号的半周期，并生成半周期延迟时钟信号;以及操作单元，其可以将所述延迟时钟信号和所述半周期 延迟时钟信号并产生输出时钟信号。