Method for treating a dielectric film
    1.
    发明授权
    Method for treating a dielectric film 失效
    电介质膜的处理方法

    公开(公告)号:US07553769B2

    公开(公告)日:2009-06-30

    申请号:US10682196

    申请日:2003-10-10

    IPC分类号: H01L21/302

    摘要: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to a CxHy containing material, wherein x and y are each integers greater than or equal to a value of unity. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue. Moreover, preparation for barrier layer and metallization of features in the film may include treating by performing sealing of sidewall surfaces of the feature to close exposed pores and provide a surface for barrier film deposition.

    摘要翻译: 用于处理电介质膜的方法和系统包括将电介质膜的至少一个表面暴露于含CxHy的材料,其中x和y各自为大于或等于一个值的整数。 介电膜可以包括具有或不具有在干蚀刻处理之后形成的蚀刻特征的孔的低介电常数膜。 作为蚀刻处理或灰化的结果,形成在电介质膜中的特征中的暴露表面可能被损坏或激活,导致污染物的保留,水分的吸收,介电常数的增加等。损坏的表面,例如这些 通过执行愈合这些表面中的至少一个来处理,例如恢复介电常数(即,降低介电常数)并清洁这些表面以去除污染物,水分或残留物。 此外,膜的特征的阻挡层和金属化的制备可以包括通过执行特征的侧壁表面的密封来封闭暴露的孔并提供用于阻挡膜沉积的表面来进行处理。

    Method and system for treating a dielectric film
    3.
    发明授权
    Method and system for treating a dielectric film 失效
    电介质膜处理方法及系统

    公开(公告)号:US07345000B2

    公开(公告)日:2008-03-18

    申请号:US11060352

    申请日:2005-02-18

    IPC分类号: H01L21/31

    摘要: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to an alkyl silane, an alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an aryl silane, an acyl silane, a cyclo siloxane, a polysilsesquioxane (PSS), an aryl siloxane, an acyl siloxane, or a halo siloxane, or any combination thereof. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue. Moreover, preparation for barrier layer and metallization of features in the film may include treating by performing sealing of sidewall surfaces of the feature to close exposed pores and provide a surface for barrier film deposition.

    摘要翻译: 用于处理电介质膜的方法和系统包括将电介质膜的至少一个表面暴露于烷基硅烷,烷氧基硅烷,烷基硅氧烷,烷氧基硅氧烷,芳基硅烷,酰基硅烷,环硅氧烷,聚倍半硅氧烷(PSS ),芳基硅氧烷,酰基硅氧烷或卤代硅氧烷,或其任何组合。 介电膜可以包括具有或不具有在干蚀刻处理之后形成的蚀刻特征的孔的低介电常数膜。 作为蚀刻处理或灰化的结果,形成在电介质膜中的特征中的暴露表面可能被损坏或激活,导致污染物的保留,水分的吸收,介电常数的增加等。损坏的表面,例如这些 通过执行愈合这些表面中的至少一个来处理,例如恢复介电常数(即,降低介电常数)并清洁这些表面以去除污染物,水分或残留物。 此外,膜的特征的阻挡层和金属化的制备可以包括通过执行特征的侧壁表面的密封来封闭暴露的孔并提供用于阻挡膜沉积的表面来进行处理。

    Method of passivating of low dielectric materials in wafer processing
    5.
    发明授权
    Method of passivating of low dielectric materials in wafer processing 失效
    在晶圆加工中钝化低介电常数材料的方法

    公开(公告)号:US07270941B2

    公开(公告)日:2007-09-18

    申请号:US10379984

    申请日:2003-03-04

    IPC分类号: G03F7/26

    摘要: A method of passivating silicon-oxide based low-k materials using a supercritical carbon dioxide passivating solution comprising a silylating agent is disclosed. The silylating agent is preferably an organosilicon compound comprising organo-groups with five carbon atoms such as hexamethyldisilazane (HMDS) and chlorotrimethylsilane (TMCS) and combinations thereof. The silicon oxide-based low-k material, in accordance with embodiments of the invention, is maintained at temperatures in a range of 40 to 200 degrees Celsius, and preferably at a temperature of about 150 degrees Celsius, and at pressures in a range of 1,070 to 9,000 psi, and preferably at a pressure of about 3,000 psi, while being exposed to the supercritical passivating solution. In accordance with further embodiments of the invention, a silicon oxide-based low-k material is simultaneously cleaned and passivated using a supercritical carbon dioxide cleaning solution.

    摘要翻译: 公开了一种使用包含甲硅烷化剂的超临界二氧化碳钝化溶液钝化基于氧化硅的低k材料的方法。 甲硅烷基化剂优选为包含具有五个碳原子的有机基团的有机硅化合物,例如六甲基二硅氮烷(HMDS)和氯代三甲基硅烷(TMCS)及其组合。 根据本发明的实施方案的基于氧化硅的低k材料保持在40至200摄氏度的温度,优选在约150摄氏度的温度下,并且在 1,070至9,000psi,优选在约3,000psi的压力下,同时暴露于超临界钝化溶液。 根据本发明的另外的实施方案,使用超临界二氧化碳清洗溶液同时清洗和钝化基于氧化硅的低k材料。

    Structure comprising amorphous carbon film and method of forming thereof
    7.
    发明授权
    Structure comprising amorphous carbon film and method of forming thereof 有权
    包含无定形碳膜的结构及其形成方法

    公开(公告)号:US07115993B2

    公开(公告)日:2006-10-03

    申请号:US10766872

    申请日:2004-01-30

    IPC分类号: H01L23/52

    摘要: A semiconductor device includes a semiconductor substrate, a film stack formed on the semiconductor substrate and having a film to be processed. A dual hard mask included in the film stack has an amorphous carbon layer and an underlying hard mask layer interposed between the amorphous carbon layer and the film to be processed, the hard mask layer does not include an amorphous carbon layer. A damascene structure for a metal interconnect is formed in the film stack. The amorphous carbon film can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The amorphous carbon film can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a top layer of a dual hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.

    摘要翻译: 半导体器件包括半导体衬底,形成在半导体衬底上并具有待处理膜的膜堆叠。 包含在膜叠层中的双重硬掩模具有无定形碳层和介于无定形碳层和待加工膜之间的下面的硬掩模层,硬掩模层不包括无定形碳层。 在薄膜叠层中形成用于金属互连的镶嵌结构。 非晶碳膜可以例如被并入单个镶嵌结构或双镶嵌结构中。 无定形碳膜可以用作用于形成互连结构的光刻掩模的一部分,或者可以在CMP期间用作双重硬掩模,化学机械抛光(CMP)阻挡层或牺牲层的顶层。