公开(公告)号：US20120115303A1

公开(公告)日：2012-05-10

申请号：US13354371

申请日：2012-01-20

申请人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC分类号： H01L21/4763 ,  H01L21/02

CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2221/1021 ,  H01L2221/1063

摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

摘要翻译： 在集成电路中形成导线的方法。 所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。 所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。

公开(公告)号：US08119522B1

公开(公告)日：2012-02-21

申请号：US12941184

申请日：2010-11-08

申请人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2221/1021 ,  H01L2221/1063

摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

公开(公告)号：US08293638B2

公开(公告)日：2012-10-23

申请号：US13354371

申请日：2012-01-20

申请人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2221/1021 ,  H01L2221/1063

摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

摘要翻译： 在集成电路中形成导线的方法。 所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。 所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。

公开(公告)号：US06797610B1

公开(公告)日：2004-09-28

申请号：US10248019

申请日：2002-12-11

申请人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC分类号： H01L214763

CPC分类号： H01L21/76802

摘要： A sublitohgraphic trench is formed in a semiconductor substrate by first forming a microtrench which is subsequently used as a mask. Filled sublithographic trenches are formed with a width corresponding to the width of the microtrenches.

摘要翻译： 通过首先形成随后用作掩模的微切口，在半导体衬底中形成子晶体学沟槽。 填充的亚光刻沟槽形成为具有对应于微锥体宽度的宽度。

公开(公告)号：US09058455B2

公开(公告)日：2015-06-16

申请号：US13354705

申请日：2012-01-20

申请人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

发明人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/48 ,  H03H9/64 ,  H01L23/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L25/16

CPC分类号： H01L41/293 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L25/16 ,  H01L27/0694 ,  H01L28/40 ,  H01L41/0815 ,  H01L41/25 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2225/06548 ,  H03H9/64

摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

摘要翻译： 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

公开(公告)号：US08569888B2

公开(公告)日：2013-10-29

申请号：US13114079

申请日：2011-05-24

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

摘要翻译： 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

公开(公告)号：US08343868B2

公开(公告)日：2013-01-01

申请号：US13005201

申请日：2011-01-12

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。

公开(公告)号：US08298860B2

公开(公告)日：2012-10-30

申请号：US13038467

申请日：2011-03-02

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L21/60

CPC分类号： G06F17/5068 ,  H01L23/3672 ,  H01L23/473 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12044

摘要： Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.

公开(公告)号：US08053901B2

公开(公告)日：2011-11-08

申请号：US12917154

申请日：2010-11-01

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L23/48

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

摘要翻译： 本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。 刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。 或者，互连结构的通孔区域可以用包含SiO 2，SiCOH或掺杂的硅酸盐玻璃的机械刚性电介质来加强。

公开(公告)号：US20110227225A1

公开(公告)日：2011-09-22

申请号：US13116622

申请日：2011-05-26

申请人： Daniel C. Edelstein ,  Edward C. Cooney, III ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Edward C. Cooney, III ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。