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1.发明授权Method for high performance inductor fabrication using a triple damascene process with copper BEOL 有权使用铜BEOL的三重镶嵌工艺的高性能电感器制造方法公开(公告)号：US07399696B2
公开(公告)日：2008-07-15
申请号：US11161415
申请日：2005-08-02
IPC分类号： H01L21/4763
CPC分类号： H01L23/5227 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric layer on a first wiring level; forming a second trench in the first dielectric layer having a second depth extending at least into a second wiring level; forming a conductor layer substantially simultaneously in the first and second trenches; and removing portions of the conductor layer overfilling the first and second trenches to form a spiral-shaped inductor in the second trench. The method may further comprise forming an interconnect structure in the first trench.
摘要翻译： 形成高性能电感器的方法包括：提供衬底; 在衬底上形成多个布线层，其中每个布线层包括介电层; 在第一布线层上形成在第一介电层中具有第一深度的第一沟槽; 在所述第一介电层中形成具有至少延伸至第二布线层的第二深度的第二沟槽; 在第一和第二沟槽中基本上同时地形成导体层; 以及去除超过第一和第二沟槽的导体层的部分，以在第二沟槽中形成螺旋形电感器。 该方法还可以包括在第一沟槽中形成互连结构。
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2.发明授权Structure and design structure for high-Q value inductor and method of manufacturing the same 有权高Q值电感器的结构和设计结构及其制造方法公开(公告)号：US08232173B2
公开(公告)日：2012-07-31
申请号：US12917029
申请日：2010-11-01
申请人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
发明人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L28/10 , H01L21/76898 , H01L23/5227 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.
摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能性表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。
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3.发明授权Structure and design structure for high-Q value inductor and method of manufacturing the same 有权高Q值电感器的结构和设计结构及其制造方法公开(公告)号：US08645898B2
公开(公告)日：2014-02-04
申请号：US13535412
申请日：2012-06-28
申请人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
发明人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
CPC分类号： H01L28/10 , H01L21/76898 , H01L23/5227 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.
摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。
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4.发明申请公开(公告)号：US20070032030A1
公开(公告)日：2007-02-08
申请号：US11161415
申请日：2005-08-02
IPC分类号： H01L21/44
CPC分类号： H01L23/5227 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric layer on a first wiring level; forming a second trench in the first dielectric layer having a second depth extending at least into a second wiring level; forming a conductor layer substantially simultaneously in the first and second trenches; and removing portions of the conductor layer overfilling the first and second trenches to form a spiral-shaped inductor in the second trench. The method may further comprise forming an interconnect structure in the first trench.
摘要翻译： 形成高性能电感器的方法包括：提供衬底; 在衬底上形成多个布线层，其中每个布线层包括介电层; 在第一布线层上形成在第一介电层中具有第一深度的第一沟槽; 在所述第一介电层中形成具有至少延伸至第二布线层的第二深度的第二沟槽; 在第一和第二沟槽中基本上同时地形成导体层; 以及去除超过第一和第二沟槽的导体层的部分，以在第二沟槽中形成螺旋形电感器。 该方法还可以包括在第一沟槽中形成互连结构。
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公开(公告)号：US20100022063A1
公开(公告)日：2010-01-28
申请号：US12180789
申请日：2008-07-28
IPC分类号： H01L21/02
CPC分类号： H01F41/041 , H01F17/0013 , H01L23/5227 , H01L23/645 , H01L24/16 , H01L24/48 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05022 , H01L2224/051 , H01L2224/05572 , H01L2224/13099 , H01L2224/16145 , H01L2224/45124 , H01L2224/48463 , H01L2224/73257 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/19011 , H01L2924/19041 , H01L2924/19104 , H01L2224/05599 , H01L2924/013 , H01L2924/00013 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Various methods of forming a passive element such as an inductor raised off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap.
摘要翻译： 提出了形成无源元件的各种方法，例如从衬底的表面上升起的电感器，以提高无源元件的性能。 可以提供第一晶片，并且从第二晶片切割无源元件。 无源元件翻转，然后对齐以接合在第一晶片上，使得无源元件由于存在诸如C4焊料凸块的芯片连接而离开第一晶片一段距离。 无源元件和第一晶片之间的间隙可以用底部填充物或空气填充。 如果使用空气，则可以使用诸如C4焊料凸块或其它已知的粘合装置之类的芯片连接来密封间隙来创建间隙周围的气密密封。
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公开(公告)号：US20100019346A1
公开(公告)日：2010-01-28
申请号：US12180810
申请日：2008-07-28
IPC分类号： H01L29/00
CPC分类号： H01L24/91 , H01F17/0006 , H01F27/027 , H01L23/645 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/94 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/16 , H01L2224/16145 , H01L2224/45124 , H01L2224/48091 , H01L2224/48463 , H01L2224/73257 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/30105 , H01L2224/05599 , H01L2924/013 , H01L2924/00013 , H01L2224/05099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： IC and design structure including various ways of raising a passive element such as an inductor off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap.
摘要翻译： 提出了IC和设计结构，其中包括从基板表面起提高无源元件（如电感器）以提高无源元件的性能的各种方式。 可以提供第一晶片，并且从第二晶片切割无源元件。 无源元件翻转，然后对齐以接合在第一晶片上，使得无源元件由于存在诸如C4焊料凸块的芯片连接而离开第一晶片一段距离。 无源元件和第一晶片之间的间隙可以用底部填充物或空气填充。 如果使用空气，则可以使用诸如C4焊料凸块或其它已知的粘合装置之类的芯片连接来密封间隙来创建间隙周围的气密密封。
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7.发明授权Methods of designing an inductor having opening enclosed within conductive line 有权设计具有封闭在导线内的开口的电感器的方法公开(公告)号：US09230725B2
公开(公告)日：2016-01-05
申请号：US13404485
申请日：2012-02-24
IPC分类号： H01F17/06 , H01F41/04 , H01F17/00 , H01L23/522 , H01L23/528 , H01L23/64 , H01L49/02 , H01F17/04 , H01F27/28
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments are provided that include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line. Embodiments of forming the inductor can include: providing an inductor design including a conductive line having at least one turn; determining a region of the conductive line that has current density below a threshold; and forming an opening in the region, the opening enclosed within the conductive line.
摘要翻译： 提供了包括设计电感器的方法的实施例。 电感器可以包括包括至少一个匝的导电线和位于导电线的区域的内部内的开口。 形成电感器的实施例可以包括：提供包括具有至少一匝的导线的电感器设计; 确定电流密度低于阈值的导线的区域; 以及在该区域中形成开口，封闭在导电线内的开口。
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8.发明授权公开(公告)号：US08193893B2
公开(公告)日：2012-06-05
申请号：US12055336
申请日：2008-03-26
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments of an inductor including a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line are disclosed. Embodiments of a related method of designing the inductor are also disclosed.
摘要翻译： 公开了一种电感器的实施例，其包括包括至少一个匝的导线和位于导线的区域内部的开口。 还公开了设计电感器的相关方法的实施例。
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9.发明申请公开(公告)号：US20090243778A1
公开(公告)日：2009-10-01
申请号：US12055336
申请日：2008-03-26
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments of an inductor including a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line are disclosed. Embodiments of a related method of designing the inductor are also disclosed.
摘要翻译： 公开了一种电感器的实施例，其包括包括至少一个匝的导线和位于导线的区域内部的开口。 还公开了设计电感器的相关方法的实施例。
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公开(公告)号：US20090146247A1
公开(公告)日：2009-06-11
申请号：US12371662
申请日：2009-02-16
申请人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
发明人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
IPC分类号： H01L29/70
CPC分类号： H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.
摘要翻译： 公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。 接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。 接地屏蔽为第一金属（M1）级别提供低电阻，非常厚的金属，用于与标准后端（BEOL）集成结合的无源RF元件。 本发明还包括形成接地屏蔽的方法。
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