公开(公告)号：US5557757A

公开(公告)日：1996-09-17

申请号：US190647

申请日：1994-02-02

Applicant: Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

Inventor： Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/423 ,  G06F13/4027

Abstract: An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.

Abstract translation: 集成处理器，采用总线接口单元，通过外部外部互连总线与复用的地址/数据线进行高性能数据传输。 可以是PCI标准总线的外围互连总线适应在集成处理器的内部总线与PCI外围设备之间的数据传输。 集成处理器还包括一个子总线控制单元，该子总线控制单元产生一组边带控制信号，这些边带控制信号允许诸如ISA总线的较低性能辅助总线的外部导出，而不需要用于次级的完整的一组外部引脚 总线上的集成处理器。 辅助总线的推导是通过由边带控制信号控制的外部数据缓冲器和外部地址锁存来实现的。 不需要用于辅助总线的集成处理器的独立地址和数据线。 因此，高性能外围设备由集成处理器以及性能更低，成本更低的外设支持，而不会显着增加集成处理器的引脚数。 因此，在支持广泛的外围设备的情况下，集成处理器的整体成本保持较低。

公开(公告)号：US5561821A

公开(公告)日：1996-10-01

申请号：US145375

申请日：1993-10-29

Applicant: Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

Inventor： Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

IPC: G06F13/28 ,  G06F13/36

CPC classification number: G06F13/28

Abstract: A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer. Since the memory access cycle and the I/O access cycle of the DMA transfer are identical to those executed by the system microprocessor, subsystems are not required to respond to specialized DMA protocols. Finally, although the DMA controller implements two-cycle DMA transfers, the DMA controller is compatible with conventional peripheral devices which assume one-cycle DMA transfer protocols.

Abstract translation: 提供了通过执行存储器访问周期和I / O访问周期来执行DMA传输的直接存储器访问控制器。 在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。 在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 DMA配置地址范围是映射DMA控制器的配置寄存器以接收初始化数据的地址值范围。 因此，可能连接到本地总线的其他外围设备将不会响应I / O访问周期。 不需要禁止地址禁止信号来禁用DMA传输中不涉及的其他I / O外围设备的地址解码器。 由于DMA传输的存储器访问周期和I / O访问周期与系统微处理器执行的存储器访问周期和I / O访问周期相同，因此子系统不需要响应专门的DMA协议。 最后，虽然DMA控制器实现了两个周期的DMA传输，但DMA控制器与传统的外围设备兼容，它们采用一个周期的DMA传输协议。

公开(公告)号：US5561819A

公开(公告)日：1996-10-01

申请号：US145376

申请日：1993-10-29

Applicant: Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

Inventor： Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

IPC: G06F13/28 ,  G06F13/36 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4018

Abstract: A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.

Abstract translation: 直接存储器访问控制器通过执行存储器访问周期和I / O访问周期来实现用于执行所需DMA传输的两周期方法。 在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。 在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 在I + 544 O访问周期期间，编码地址值的较低的两位，以向外围设备提供字节通道信息。 外围设备响应地在指定的字节通道处接收或提供数据。 结果，可能连接到本地总线的外围设备将不会响应I / O访问周期，而编码字节通道信息被提供给期望的外围设备，而不需要专用字节选择线。

公开(公告)号：US5905898A

公开(公告)日：1999-05-18

申请号：US605873

申请日：1996-02-23

Applicant: Qadeer A. Qureshi ,  Dan S. Mudgett ,  James R. MacDonald ,  Douglas D. Gephardt ,  Rodney W. Schmidt

Inventor： Qadeer A. Qureshi ,  Dan S. Mudgett ,  James R. MacDonald ,  Douglas D. Gephardt ,  Rodney W. Schmidt

IPC: G06F13/26 ,  G06F15/17 ,  G06F3/00

CPC classification number: G06F13/26 ,  G06F15/17

Abstract: A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.

Abstract translation: 提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。 可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。 中断请求识别码分配给每个中断请求并存储在嵌套缓冲区中。 用于引用中断请求的中断请求标识代码按其优先顺序存储。 每个嵌套缓冲区只需要等于优先级数量的条目数。

公开(公告)号：US5894577A

公开(公告)日：1999-04-13

申请号：US125336

申请日：1993-09-22

Applicant: James R MacDonald ,  Douglas D. Gephardt ,  Dan S. Mudgett

Inventor： James R MacDonald ,  Douglas D. Gephardt ,  Dan S. Mudgett

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/48 ,  G06F13/24 ,  G06F13/26 ,  G06F9/46

CPC classification number: G06F1/3215 ,  G06F1/3237 ,  G06F1/325 ,  G06F1/3287 ,  G06F13/24 ,  G06F13/26 ,  Y02B60/1221 ,  Y02B60/1282 ,  Y02B60/32

Abstract: An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.

Abstract translation: 中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。 还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。 提供在线寄存器用于存储由微处理器服务的任何请求线的标识。 在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。 功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。 使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。 通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。

公开(公告)号：US5765003A

公开(公告)日：1998-06-09

申请号：US671831

申请日：1996-10-09

Applicant: James R. MacDonald ,  Douglas D. Gephardt ,  Dan S. Mudgett

Inventor： James R. MacDonald ,  Douglas D. Gephardt ,  Dan S. Mudgett

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/48 ,  G06F13/24 ,  G06F13/26

CPC classification number: G06F1/3215 ,  G06F1/3237 ,  G06F1/325 ,  G06F1/3287 ,  G06F13/24 ,  G06F13/26 ,  Y02B60/1221 ,  Y02B60/1282 ,  Y02B60/32

Abstract: An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.

Abstract translation: 中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。 还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。 提供在线寄存器用于存储由微处理器服务的任何请求线的标识。 在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。 功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。 使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。 通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。

公开(公告)号：US5655142A

公开(公告)日：1997-08-05

申请号：US705884

申请日：1996-08-28

Applicant: Douglas D. Gephardt ,  Dan S. Mudgett

Inventor： Douglas D. Gephardt ,  Dan S. Mudgett

IPC: G06F13/38 ,  G06F13/42 ,  G06F15/78 ,  G06F13/24

CPC classification number: G06F13/4217 ,  G06F13/423 ,  G06F15/7832

Abstract: An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus interface unit is further provided to interface between the CPU local bus and a PCI standard multiplexed peripheral bus. The CPU core, the memory controller, the direct memory access controller, the interrupt controller, and the bus interface unit are all incorporated on a common integrated circuit chip. A local bus control unit is further provided that is capable of generating a loading signal and an address strobe signal synchronously with certain bus cycles that are executed on the PCI bus. The local bus control unit allows external peripheral devices that are compatible with the CPU local bus protocols to be connected through the PCI bus. A latch is coupled to the multiplexed address/data (A/D) lines of the PCI bus and includes a set of output lines coupled to the address input lines of the externally connected peripheral device. The external latch is latched by the loading signal. The cycle definition signals of the PCI bus are further latched within the external latch to provide memory/IO and read/write signals to the external peripheral device. The data lines of the peripheral device may be connected directly to the multiplexed address/data lines of the PCI bus.

Abstract translation: 提供了一种集成处理器，其包括CPU核心，耦合到CPU核心的本地总线以及耦合到本地总线的诸如存储器控制器，直接存储器访问控制器和中断控制器的各种外设。 还提供总线接口单元以在CPU本地总线和PCI标准复用的外围总线之间进行接口。 CPU核心，存储器控制器，直接存储器访问控制器，中断控制器和总线接口单元都被并入公共集成电路芯片。 还提供了本地总线控制单元，其能够与在PCI总线上执行的某些总线周期同步地产生加载信号和地址选通信号。 本地总线控制单元允许通过PCI总线连接与CPU本地总线协议兼容的外部外设。 锁存器耦合到PCI总线的复用的地址/数据（A / D）线，并且包括耦合到外部连接的外围设备的地址输入线的一组输出线。 外部锁存器被加载信号锁存。 PCI总线的周期定义信号进一步锁存在外部锁存器内，以向外部外围设备提供存储/ IO和读/写信号。 外围设备的数据线可以直接连接到PCI总线的复用地址/数据线。

公开(公告)号：US06357024B1

公开(公告)日：2002-03-12

申请号：US09132334

申请日：1998-08-12

Applicant: Drew J. Dutton ,  Dan S. Mudgett ,  Scott A. White

Inventor： Drew J. Dutton ,  Dan S. Mudgett ,  Scott A. White

IPC: G06F1100

CPC classification number: G06F11/1654 ,  G06F11/1641 ,  G06F11/165 ,  G06F2201/83

Abstract: An electronic system and method are presented for the implementation of functional redundancy checking (FRC) by comparing “signatures” produced by two different electronic devices, for example central processing units (CPUs). The signatures include a relatively small number of signals which reflect an internal state of each CPU. The electronic system includes a first and second CPU. Each CPU is configured to execute instructions and produce output signals. The first and second CPUs are preferably identical and execute instructions simultaneously such that their internal states and produced output signals should be the same at any given time. Each CPU includes a signature generator for generating the signature. The electronic system also includes a compare unit coupled to receive the signatures. The compare unit compares the signatures and produces an error signal if the signatures are not identical. The electronic system may be a computer system, further including a system bus and chip set logic. The system bus is adapted for coupling to one or more peripheral devices. The chip set logic is coupled between the first and second CPUs and the system bus, and functions as an interface between the first and second CPUs and the system bus. The first and second CPU are coupled to the chip set logic via separate processor buses. At least a portion of the signal lines of the separate processor buses are “point-to-point”, enabling the processor buses to achieve relatively high data transfer rates.

Abstract translation: 通过比较由两个不同的电子设备（例如中央处理单元（CPU））产生的“签名”来呈现用于实现功能冗余检查（FRC）的电子系统和方法。 签名包括反映每个CPU的内部状态的相对较少数量的信号。 该电子系统包括第一和第二CPU。 每个CPU配置为执行指令并产生输出信号。 第一和第二CPU优选地是相同的并且同时执行指令，使得它们的内部状态和产生的输出信号在任何给定的时间应该相同。 每个CPU包括用于生成签名的签名生成器。 电子系统还包括耦合以接收签名的比较单元。 比较单元比较签名并且如果签名不相同则产生错误信号。 电子系统可以是计算机系统，还包括系统总线和芯片组逻辑。 系统总线适于耦合到一个或多个外围设备。 芯片组逻辑耦合在第一和第二CPU与系统总线之间，并且用作第一和第二CPU与系统总线之间的接口。 第一和第二CPU通过单独的处理器总线耦合到芯片组逻辑。 单独处理器总线的信号线的至少一部分是“点到点”，使得处理器总线能够实现相对较高的数据传输速率。

公开(公告)号：US5099140A

公开(公告)日：1992-03-24

申请号：US575594

申请日：1990-08-31

Applicant: Dan S. Mudgett

Inventor： Dan S. Mudgett

IPC: G06F1/08 ,  H03K5/13 ,  H03K5/26

CPC classification number: G06F1/08 ,  H03K5/13 ,  H03K5/26

Abstract: A clock source selector provides at least one set of clock signals selected from a plurality of clock sources and a synchronized transition from an old clock source to a new clock source. The clock source selector includes a gate having an output for providing the clock signals, a selector coupled between the plurality of clock sources and the gate for providing the gate with clock signals from selected ones of the clock sources responsive to selection signals, a detector for detecting a change in the selection signals from an old clock source to a new clock source, and a synchronizing circuit responsive to the detector for disabling the gate in synchronism with the old clock source and thereafter enabling the gate in synchronism with the new clock source.

Abstract translation: 时钟源选择器提供从多个时钟源中选择的至少一组时钟信号和从旧时钟源到新时钟源的同步转换。 时钟源选择器包括具有用于提供时钟信号的输出端的栅极，耦合在多个时钟源和栅极之间的选择器，用于响应于选择信号向所选择的时钟源提供来自选择的时钟源的时钟信号; 检测从旧时钟源到新时钟源的选择信号的变化，以及响应于检测器的同步电路，用于与旧时钟源同步地禁用门，此后使得门能够与新的时钟源同步。

公开(公告)号：US06775749B1

公开(公告)日：2004-08-10

申请号：US10059934

申请日：2002-01-29

Applicant: Dan S. Mudgett ,  Mark T. Fox

Inventor： Dan S. Mudgett ,  Mark T. Fox

IPC: G06F1316

CPC classification number: G06F12/0831 ,  G06F2212/507

Abstract: A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in response, to send a probe to determine whether any of the other caches contain a copy of the requested data. Some time after sending the probe, the cache controller may provide a speculative response to the cache fill request to the requesting device. By delaying providing the speculative response until some time after the probes are sent, it may become more likely that the responses to the probes will be received in time to validate the speculative response.

Abstract translation: 计算机系统可以包括几个高速缓存，每个缓存被耦合以从共享存储器接收数据。 高速缓存一致性机制可以被配置为接收缓存填充请求，并且作为响应，发送探测以确定其他高速缓存中是否包含所请求数据的副本。 在发送探测器之后的某个时间，缓存控制器可以向请求设备提供对缓存填充请求的推测响应。 通过在发送探针之后延迟提供推测性响应，可能会及时收到对探针的响应以验证推测性响应。